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| author |   Yash Shah <yash.shah@sifive.com> | 2019-05-06 16:18:40 +0530 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@sifive.com> | 2019-05-16 20:42:13 -0700 |
| commit | a967a289f16969527a8a41e261695c639a69bee4 (patch) | |
| tree | eda00cc7ecc719a9ed5e9cb82d27b64fb929d4fa /scripts/gdb/linux/utils.py | |
| parent | RISC-V: Add DT documentation for SiFive L2 Cache Controller (diff) | |
| download | wireguard-linux-a967a289f16969527a8a41e261695c639a69bee4.tar.xz wireguard-linux-a967a289f16969527a8a41e261695c639a69bee4.zip | |
RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
The driver currently supports only SiFive FU540-C000 platform.
The initial version of L2 cache controller driver includes:
- Initial configuration reporting at boot up.
- Support for ECC related functionality.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
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