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| author |   Miquel Raynal <miquel.raynal@bootlin.com> | 2019-07-31 14:21:25 +0200 |
|---|---|---|
| committer |   Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-08-27 16:20:16 +0200 |
| commit | ce55522c035e98803832eff8938f621f25b0f4f1 (patch) | |
| tree | 63caacc8573c0ef7c4e97f1fc3ed3a6e2aeb0d9c /scripts/gdb/linux/utils.py | |
| parent | arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes (diff) | |
| download | wireguard-linux-ce55522c035e98803832eff8938f621f25b0f4f1.tar.xz wireguard-linux-ce55522c035e98803832eff8938f621f25b0f4f1.zip | |
arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
Fill-in the missing PCIe phys/phy-names DT properties of Armada 7k/8k
based boards.
The MacchiatoBin is a bit particular as the Armada8k-PCI IP supports
x4 link widths and in this case the PHY for each lane must be
referenced.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions