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| author |   Li Qiang <liqiang01@kylinos.cn> | 2024-07-09 14:36:38 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2024-07-10 14:15:54 -0700 |
| commit | 1f7a04a0e673c19cc10bf4039047e11367ac5735 (patch) | |
| tree | f9e07b27c32a1459157ec6a4738379c37b38ed96 /scripts/generate_rust_analyzer.py | |
| parent | Merge tag 'riscv-sg2042-clk-for-v6.11' of https://github.com/sophgo/linux into clk-sophgo (diff) | |
| download | wireguard-linux-1f7a04a0e673c19cc10bf4039047e11367ac5735.tar.xz wireguard-linux-1f7a04a0e673c19cc10bf4039047e11367ac5735.zip | |
clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()
In general it's a good idea to avoid using bare unreachable() because it
introduces undefined behavior in compiled code. but it caused a compilation warning,
Using BUG() instead of unreachable() to resolve compilation warnings.
Fixes the following warnings:
drivers/clk/sophgo/clk-cv18xx-ip.o: warning: objtool: mmux_round_rate() falls through to next function bypass_div_round_rate()
Fixes: 80fd61ec46124 ("clk: sophgo: Add clock support for CV1800 SoC")
Signed-off-by: Li Qiang <liqiang01@kylinos.cn>
Link: https://lore.kernel.org/r/c8e66d51f880127549e2a3e623be6787f62b310d.1720506143.git.liqiang01@kylinos.cn
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions