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| author |   Stephen Boyd <sboyd@kernel.org> | 2024-07-08 11:46:31 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-07-08 11:46:31 -0700 |
| commit | 54cb3bb483379b0c070528974843e06aecbc9390 (patch) | |
| tree | 1e97f5ba442d4bb111486b33868403b343f3bce4 /scripts/generate_rust_analyzer.py | |
| parent | Linux 6.10-rc1 (diff) | |
| parent | clk: sophgo: Add SG2042 clock driver (diff) | |
| download | wireguard-linux-54cb3bb483379b0c070528974843e06aecbc9390.tar.xz wireguard-linux-54cb3bb483379b0c070528974843e06aecbc9390.zip | |
Merge tag 'riscv-sg2042-clk-for-v6.11' of https://github.com/sophgo/linux into clk-sophgo
Pull RISC-V SG2042 clock driver changes from Chen Wang:
- Add sg2042 clk driver
* tag 'riscv-sg2042-clk-for-v6.11' of https://github.com/sophgo/linux:
clk: sophgo: Add SG2042 clock driver
dt-bindings: clock: sophgo: add clkgen for SG2042
dt-bindings: clock: sophgo: add RP gate clocks for SG2042
dt-bindings: clock: sophgo: add pll clocks for SG2042
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions