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| author |   Lukasz Czechowski <lukasz.czechowski@thaumatec.com> | 2025-01-21 13:56:03 +0100 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2025-02-03 09:14:34 +0100 |
| commit | 4eee627ea59304cdd66c5d4194ef13486a6c44fc (patch) | |
| tree | 7e65cc8cfff72b830827223aea6838ff2396cebc /scripts/generate_rust_analyzer.py | |
| parent | arm64: dts: rockchip: change eth phy mode to rgmii-id for orangepi r1 plus lts (diff) | |
| download | wireguard-linux-4eee627ea59304cdd66c5d4194ef13486a6c44fc.tar.xz wireguard-linux-4eee627ea59304cdd66c5d4194ef13486a6c44fc.zip | |
arm64: dts: rockchip: Move uart5 pin configuration to px30 ringneck SoM
In the PX30-uQ7 (Ringneck) SoM, the hardware CTS and RTS pins for
uart5 cannot be used for the UART CTS/RTS, because they are already
allocated for different purposes. CTS pin is routed to SUS_S3#
signal, while RTS pin is used internally and is not available on
Q7 connector. Move definition of the pinctrl-0 property from
px30-ringneck-haikou.dts to px30-ringneck.dtsi.
This commit is a dependency to next commit in the patch series,
that disables DMA for uart5.
Cc: stable@vger.kernel.org
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Link: https://lore.kernel.org/r/20250121125604.3115235-2-lukasz.czechowski@thaumatec.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions