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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2024-11-25 13:40:58 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-11-25 13:40:58 -0600 |
| commit | 5c8bd7f27704f1c8ba088f719a4346d4f51383a8 (patch) | |
| tree | b08661db2cad6e65de87067cee33887bb7f2afd1 /scripts/generate_rust_analyzer.py | |
| parent | Merge branch 'pci/controller/imx6' (diff) | |
| parent | PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds (diff) | |
| download | wireguard-linux-5c8bd7f27704f1c8ba088f719a4346d4f51383a8.tar.xz wireguard-linux-5c8bd7f27704f1c8ba088f719a4346d4f51383a8.zip | |
Merge branch 'pci/controller/j721e'
- Add PCIe support for J722S SoC (Siddharth Vadapalli)
- Delay PCIE_T_PVPERL_MS (100 ms), not just PCIE_T_PERST_CLK_US (100 us),
before deasserting PERST# to ensure power and refclk are stable
(Siddharth Vadapalli)
* pci/controller/j721e:
PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds
PCI: j721e: Add PCIe support for J722S SoC
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions