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| author |   Sunil V L <sunilvl@ventanamicro.com> | 2022-05-27 10:47:41 +0530 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-07-19 16:39:09 -0700 |
| commit | 62750eae410cf20b7d040395064bac547cfdf540 (patch) | |
| tree | 7f4428e10aff0ef3761c09d7823314964bf85ade /scripts/generate_rust_analyzer.py | |
| parent | riscv: spinwait: Fix hartid variable type (diff) | |
| download | wireguard-linux-62750eae410cf20b7d040395064bac547cfdf540.tar.xz wireguard-linux-62750eae410cf20b7d040395064bac547cfdf540.zip | |
riscv: smp: Add 64bit hartid support on RV64
The hartid can be a 64bit value on RV64 platforms.
Modify the hartid parameter in riscv_hartid_to_cpuid() as
unsigned long so that it can hold 64bit value on RV64 platforms.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20220527051743.2829940-4-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions