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| author |   Gabriel Fernandez <gabriel.fernandez@foss.st.com> | 2022-06-24 11:27:14 +0200 |
|---|---|---|
| committer |   Alexandre Torgue <alexandre.torgue@foss.st.com> | 2022-07-04 09:10:24 +0200 |
| commit | cfd7ea394cd3b70ba4d9d87ee7b88e37459036b0 (patch) | |
| tree | 4bac3f282a8bc24cc6d4c110f73b5dc210dc8209 /scripts/generate_rust_analyzer.py | |
| parent | ARM: dts: stm32: use the correct clock source for CEC on stm32mp151 (diff) | |
| download | wireguard-linux-cfd7ea394cd3b70ba4d9d87ee7b88e37459036b0.tar.xz wireguard-linux-cfd7ea394cd3b70ba4d9d87ee7b88e37459036b0.zip | |
ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board
LSE clock is provided by SCMI.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions