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| author |   Palmer Dabbelt <palmer@rivosinc.com> | 2024-07-24 07:33:41 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-07-26 05:50:48 -0700 |
| commit | ec1dc56b54d679cbfaa7ef7abbf23bdeac029af1 (patch) | |
| tree | 20d26b088930ef3f056ccc98adfe331531816e6b /scripts/generate_rust_analyzer.py | |
| parent | riscv: enable HAVE_ARCH_STACKLEAK (diff) | |
| parent | RISC-V: ACPI: Enable SPCR table for console output on RISC-V (diff) | |
| download | wireguard-linux-ec1dc56b54d679cbfaa7ef7abbf23bdeac029af1.tar.xz wireguard-linux-ec1dc56b54d679cbfaa7ef7abbf23bdeac029af1.zip | |
Merge patch "Enable SPCR table for console output on RISC-V"
Sia Jee Heng <jeeheng.sia@starfivetech.com> says:
The ACPI SPCR code has been used to enable console output for ARM64 and
X86. The same code can be reused for RISC-V. Furthermore, SPCR table is
mandated for headless system as outlined in the RISC-V BRS
Specification, chapter 6.
* b4-shazam-merge:
RISC-V: ACPI: Enable SPCR table for console output on RISC-V
Link: https://lore.kernel.org/r/20240502073751.102093-1-jeeheng.sia@starfivetech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions