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| author |   Sam Protsenko <semen.protsenko@linaro.org> | 2023-02-22 22:21:30 -0600 |
|---|---|---|
| committer |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-03-06 16:57:15 +0100 |
| commit | f2819ea168ef6a66c6b91fc30ce659a030268add (patch) | |
| tree | 28deb79cd8f82bb672da8a2cf68acee8e38bf570 /scripts/generate_rust_analyzer.py | |
| parent | Merge branch 'for-v6.4/clk-exynos850-dt-binding' into next/clk (diff) | |
| download | wireguard-linux-f2819ea168ef6a66c6b91fc30ce659a030268add.tar.xz wireguard-linux-f2819ea168ef6a66c6b91fc30ce659a030268add.zip | |
clk: samsung: clk-pll: Implement pll0818x PLL type
pll0818x PLL is used in Exynos850 SoC for CMU_G3D PLL. Operation-wise,
pll0818x is the same as pll0822x. The only difference is:
- pl0822x is integer PLL with Middle FVCO (950 to 2400 MHz)
- pl0818x is integer PLL with Low FVCO (600 to 1200 MHz)
Add pll0818x type as an alias to pll0822x.
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223042133.26551-4-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions