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| author |   Xianwei Zhao <xianwei.zhao@amlogic.com> | 2024-05-22 16:27:25 +0800 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2024-06-04 10:27:23 +0200 |
| commit | fc1c7f941c71460a730a449f76764d883e270cba (patch) | |
| tree | 871dc70f002de5c15b4ee7507be9cd49f7eabbf5 /scripts/generate_rust_analyzer.py | |
| parent | dt-bindings: clock: add Amlogic C3 SCMI clock controller support (diff) | |
| download | wireguard-linux-fc1c7f941c71460a730a449f76764d883e270cba.tar.xz wireguard-linux-fc1c7f941c71460a730a449f76764d883e270cba.zip | |
dt-bindings: clock: add Amlogic C3 peripherals clock controller
Add the peripherals clock controller dt-bindings for Amlogic C3 SoC family
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Co-developed-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240522082727.3029656-4-xianwei.zhao@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions