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| author |   Ben Zong-You Xie <ben717@andestech.com> | 2025-07-11 21:30:23 +0800 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2025-07-21 16:51:52 +0200 |
| commit | 9d462f56db7a0fdb0c814b34a6f9bdd01ebc23f5 (patch) | |
| tree | 04b50e5c4d81469673827b846edb9e1dfea7bff6 /tools/perf/scripts/python/Perf-Trace-Util/lib | |
| parent | riscv: dts: andes: add QiLai SoC device tree (diff) | |
| download | wireguard-linux-9d462f56db7a0fdb0c814b34a6f9bdd01ebc23f5.tar.xz wireguard-linux-9d462f56db7a0fdb0c814b34a6f9bdd01ebc23f5.zip | |
riscv: dts: andes: add Voyager board device tree
Introduce the device tree support for Voyager development board.
Currently only support booting into console with only uart,
other features will be added later.
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-8-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib')
0 files changed, 0 insertions, 0 deletions