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| author |   Stephen Boyd <sboyd@kernel.org> | 2025-07-21 10:17:51 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-07-21 10:17:51 -0700 |
| commit | e4b2a0c2b9be6d10b0e50a7485fe9f569a6f2436 (patch) | |
| tree | 77538878cf16aa407c41087dd14ff0c78cb7d2db /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | dt-bindings: clock: mediatek: Add #reset-cells property for MT8188 (diff) | |
| parent | clk: sunxi-ng: v3s: Fix TCON clock parents (diff) | |
| download | wireguard-linux-e4b2a0c2b9be6d10b0e50a7485fe9f569a6f2436.tar.xz wireguard-linux-e4b2a0c2b9be6d10b0e50a7485fe9f569a6f2436.zip | |
Merge tag 'sunxi-clk-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull Allwinner clock fixes from Chen-Yu Tsai:
- Mark A523 MBUS clock as critical
- Fix names of CSI related clocks on V3s
This includes changes to the driver, DT bindings and DT files.
- Fix parents of TCON clock on V3s
* tag 'sunxi-clk-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: v3s: Fix TCON clock parents
clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name
clk: sunxi-ng: v3s: Fix CSI SCLK clock name
clk: sunxi-ng: a523: Mark MBUS clock as critical
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions