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| author |   Jouni Högander <jouni.hogander@intel.com> | 2025-04-23 13:27:04 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2025-04-28 12:11:18 +0300 |
| commit | 2af5615a5ba1aac2a356aa4cd9fc02e78c037092 (patch) | |
| tree | 8e28f9b28c334f603e61807ad6f6a4f527e37fc4 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/display: Ensure enough lines between delayed VBlank and VBlank (diff) | |
| download | wireguard-linux-2af5615a5ba1aac2a356aa4cd9fc02e78c037092.tar.xz wireguard-linux-2af5615a5ba1aac2a356aa4cd9fc02e78c037092.zip | |
drm/i915/psr: Move PSR workaround to intel_psr.c
Logical place for PSR workaround needing vblank delay is in
intel_psr_min_vblank_delay. Move it there.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://lore.kernel.org/r/20250423102704.1368310-2-jouni.hogander@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions