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| author |   Runyang Chen <runyang.chen@mediatek.com> | 2023-05-25 15:50:10 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2023-06-12 18:21:01 -0700 |
| commit | 2cf4ec53446fa5ab6f860b10a4d825311c40518d (patch) | |
| tree | e4d57e3e1517bbbd36d59bf510c67b297fcabf45 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks (diff) | |
| download | wireguard-linux-2cf4ec53446fa5ab6f860b10a4d825311c40518d.tar.xz wireguard-linux-2cf4ec53446fa5ab6f860b10a4d825311c40518d.zip | |
dt-bindings: reset: mt8188: add thermal reset control bit
To support reset of infra_ao, add the index of infra_ao reset of thermal
for MT8188.
Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230525075011.7032-2-runyang.chen@mediatek.com
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions