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| author |   Takahiro Kuwano <Takahiro.Kuwano@infineon.com> | 2023-07-26 10:52:50 +0300 |
|---|---|---|
| committer |   Tudor Ambarus <tudor.ambarus@linaro.org> | 2023-07-26 12:39:11 +0300 |
| commit | 362f786ea00aa21a19ab4f1f836aa0bf9d0aab88 (patch) | |
| tree | f9d2d647141cd3f17897a279e6d249930612cf11 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | mtd: spi-nor: spansion: prepare octal dtr methods for multi chip support (diff) | |
| download | wireguard-linux-362f786ea00aa21a19ab4f1f836aa0bf9d0aab88.tar.xz wireguard-linux-362f786ea00aa21a19ab4f1f836aa0bf9d0aab88.zip | |
mtd: spi-nor: spansion: switch set_octal_dtr method to use vreg_offset
All the Infineon flashes that currently support octal DTR mode
define the optional SCCR SFDP table, thus all retrieve vreg_offset.
Switch all the available octal DTR Infineon flashes to use the
volatile register offset to set the configuration registers. The goal
is to have a single pair of methods for both single/multi-chip package
devices.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Link: https://lore.kernel.org/r/20230726075257.12985-5-tudor.ambarus@linaro.org
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions