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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-28 12:45:33 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-03-28 14:29:50 +0200 |
| commit | 403fe77e22eb72c962c3889efc9d4fa62e454737 (patch) | |
| tree | efbac564b4f030f02fa4aa52419e967977bbc1c8 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: alt: Correct clock of DU1 (diff) | |
| download | wireguard-linux-403fe77e22eb72c962c3889efc9d4fa62e454737.tar.xz wireguard-linux-403fe77e22eb72c962c3889efc9d4fa62e454737.zip | |
ARM: dts: silk: Correct clock of DU1
The second channel of the display unit uses a different module clock
than the first channel.
Fixes: 84e734f497cd48f6 ("ARM: dts: silk: add DU DT support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions