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| author |   Mark Brown <broonie@kernel.org> | 2024-03-29 01:32:01 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2024-03-29 01:32:01 +0000 |
| commit | 439c69f80961b75d5b52fda08073ee2af63e731d (patch) | |
| tree | d15130e0a1ed1a3a8f6b818cd92fcc1e151ee9cd /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: imx8qxp add asrc and sai (diff) | |
| parent | ASoC: Intel: sof_cs42l42: add mtl_cs42l42_def for mtl boards (diff) | |
| download | wireguard-linux-439c69f80961b75d5b52fda08073ee2af63e731d.tar.xz wireguard-linux-439c69f80961b75d5b52fda08073ee2af63e731d.zip | |
ASoC: Intel: boards: updates for 6.10 - part3
Merge series from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:
This last part is the continuation of Brent Lu's cleanups. Multiple
quirks have been removed to use "default" configurations and
ACPI-based detection of codecs and selection of topology files.
This cleanup has been done in multiple steps/phases since Fall 2023,
thanks Brent for this contribution!
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