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| author |   Jernej Skrabec <jernej.skrabec@siol.net> | 2019-01-28 21:55:02 +0100 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@bootlin.com> | 2019-01-29 10:07:26 +0100 |
| commit | 4571a7d814add6bddc91594c0d5862df1504c183 (patch) | |
| tree | 87b6d52c59db1e66b8c67587a9618db46d944b40 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: allwinner: a64: Add A64 CSI controller (diff) | |
| download | wireguard-linux-4571a7d814add6bddc91594c0d5862df1504c183.tar.xz wireguard-linux-4571a7d814add6bddc91594c0d5862df1504c183.zip | |
dt-bindings: sram: sunxi: Add compatible for the H6 SRAM C1
This introduces a new compatible for the H6 SRAM C1 section, that is
compatible with the SRAM C1 section as found on the A10.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions