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authorStephen Boyd <sboyd@kernel.org>2024-01-09 11:55:47 -0800
committerStephen Boyd <sboyd@kernel.org>2024-01-09 11:55:47 -0800
commit4f964cfef39d48a8e6748847df9a1ed310b96c4e (patch)
treeef4e3c36c4b2b528dde9a29cd6dbc89a31370664 /tools/perf/scripts/python/export-to-postgresql.py
parentMerge branches 'clk-zynq', 'clk-xilinx' and 'clk-stm' into clk-next (diff)
parentclk: rs9: Add support for 9FGV0841 (diff)
downloadwireguard-linux-4f964cfef39d48a8e6748847df9a1ed310b96c4e.tar.xz
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Merge branch 'clk-rs9' into clk-next
* clk-rs9: clk: rs9: Add support for 9FGV0841 clk: rs9: Replace model check with bitshift from chip data clk: rs9: Limit check to vendor ID in VID register dt-bindings: clk: rs9: Add 9FGV0841
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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