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| author |   Martin Leung <Martin.Leung@amd.com> | 2022-09-27 18:13:38 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-10-10 17:15:08 -0400 |
| commit | 5ff32b52995155f91de582124485d0f0f8881363 (patch) | |
| tree | 7de6b5e9327c1c7048563fa483a894f9cecf792b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: properly configure DCFCLK when enable/disable Freesync (diff) | |
| download | wireguard-linux-5ff32b52995155f91de582124485d0f0f8881363.tar.xz wireguard-linux-5ff32b52995155f91de582124485d0f0f8881363.zip | |
drm/amd/display: zeromem mypipe heap struct before using it
[Why & How]
bug was caused when moving variable from stack to
heap because it was reusable and garbage was left
over, so we need to zero mem
Fixes: 7acc487ab57e ("drm/amd/display: reduce stack size in dcn32 dml (v2)")
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Martin Leung <Martin.Leung@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions