diff options
author | 2024-01-09 11:52:28 -0800 | |
---|---|---|
committer | 2024-01-09 11:52:28 -0800 | |
commit | 76a2ee33762e18eef15f2677f70b251a1839f0c5 (patch) | |
tree | 6ecb2905907419680ec31fe0c022fcab661e2f14 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge tag 'renesas-clk-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas (diff) | |
parent | Merge tag 'v6.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip (diff) | |
parent | Merge tag 'sunxi-clk-for-6.8-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner (diff) | |
parent | clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw (diff) | |
download | wireguard-linux-76a2ee33762e18eef15f2677f70b251a1839f0c5.tar.xz wireguard-linux-76a2ee33762e18eef15f2677f70b251a1839f0c5.zip |
Merge branches 'clk-renesas', 'clk-rockchip', 'clk-allwinner' and 'clk-cleanup' into clk-next
* clk-renesas:
clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1
clk: renesas: rzg2l: Check reset monitor registers
clk: renesas: r9a08g045: Add IA55 pclk and its reset
clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()
clk: renesas: r8a779g0: Add PCIe clocks
clk: renesas: r8a779g0: Add EtherTSN clock
* clk-rockchip:
clk: rockchip: rk3568: Mark pclk_usb as critical
clk: rockchip: rk3568: Add PLL rate for 126.4MHz
clk: rockchip: rk3568: Add PLL rate for 115.2MHz
* clk-allwinner:
clk: sunxi-ng: nkm: remove redundant initialization of tmp_parent
* clk-cleanup:
clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw
clk: si5341: fix an error code problem in si5341_output_clk_set_rate
clk: microchip: mpfs-ccc: replace include of asm-generic/errno-base.h
clk: rs9: Fix DIF OEn bit placement on 9FGV0241
clk: mmp: pxa168: Fix memory leak in pxa168_clk_init()
clk: hi3620: Fix memory leak in hi3620_mmc_clk_init()
clk: sp7021: fix return value check in sp7021_clk_probe()