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author | 2017-12-09 16:59:16 +0300 | |
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committer | 2017-12-20 12:41:44 -0800 | |
commit | 7bde846d0957fb81ac0bf8c4e2cab284a1da34e0 (patch) | |
tree | f42db7f5eda26e093ab928df518e8632f5f1bd4d /tools/perf/scripts/python/export-to-postgresql.py | |
parent | ARC: [plat-hsdk]: Set initial core pll output frequency (diff) | |
download | wireguard-linux-7bde846d0957fb81ac0bf8c4e2cab284a1da34e0.tar.xz wireguard-linux-7bde846d0957fb81ac0bf8c4e2cab284a1da34e0.zip |
ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code
Get rid of core pll frequency set in platform code as we set it via
device tree using 'assigned-clock-rates' property.
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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