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| author |   Chris Brandt <chris.brandt@renesas.com> | 2017-03-30 14:16:09 -0700 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-04-03 06:16:35 -0400 |
| commit | 91a7c50cb4fabfba218549dfa84356069918bfbf (patch) | |
| tree | 4c6689c8c771aaf86cd6a4317f55d51e4324fc72 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: silk: Correct clock of DU1 (diff) | |
| download | wireguard-linux-91a7c50cb4fabfba218549dfa84356069918bfbf.tar.xz wireguard-linux-91a7c50cb4fabfba218549dfa84356069918bfbf.zip | |
ARM: dts: r7s72100: fix ethernet clock parent
Technically, the Ethernet block is run off the 133MHz Bus (B) clock, not
the 33MHz Peripheral 0 (P0) clock.
Fixes: 969244f9c720 ("ARM: dts: r7s72100: add ethernet clock to device tree")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions