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| author |   Graham Moore <grmoore@opensource.altera.com> | 2016-03-08 17:02:50 +0000 |
|---|---|---|
| committer |   Dinh Nguyen <dinguyen@kernel.org> | 2016-04-11 13:58:34 -0500 |
| commit | a1e89630ea8b3797f8ecbdc95e210e29ea461bfa (patch) | |
| tree | 26166004615b10656d0ed51baf12673145865f81 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: socfpga: add the clk-phase property for sd/mmc clock (diff) | |
| download | wireguard-linux-a1e89630ea8b3797f8ecbdc95e210e29ea461bfa.tar.xz wireguard-linux-a1e89630ea8b3797f8ecbdc95e210e29ea461bfa.zip | |
ARM: dts: socfpga: Add missing clock and interrupt fields for Arria10 DMA
The PL330 DMA driver will not load on Arria10 without devicetree entries
for clocks and clock_names. This patch adds those entries. It also adds
the ninth interrupt, which is required for error detection.
Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions