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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2016-06-10 12:06:45 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2016-07-07 10:21:18 +0200 |
| commit | a5547642a4e08c98edeaf4b62f6da0ac8ed2f6bd (patch) | |
| tree | f565d7e3d9b1b9959aaea16f68ee48c2e261ad8c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge tag 'clk-renesas-for-v4.8-tag2' into HEAD (diff) | |
| download | wireguard-linux-a5547642a4e08c98edeaf4b62f6da0ac8ed2f6bd.tar.xz wireguard-linux-a5547642a4e08c98edeaf4b62f6da0ac8ed2f6bd.zip | |
arm64: dts: r8a7795: Add missing blank lines between cpu nodes
For consistency with a57_0/a57_1 cpu nodes, and all other nodes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions