diff options
| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-10 09:27:38 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-10 09:27:38 +0200 |
| commit | a96aed0636d49f39e4c9eb85ef7c8630e12e3421 (patch) | |
| tree | a50b259482e64a5bc055450acb09c3d2a71a60b7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: rzg2l: Add divider clock for RZ/G3S (diff) | |
| parent | dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC (diff) | |
| download | wireguard-linux-a96aed0636d49f39e4c9eb85ef7c8630e12e3421.tar.xz wireguard-linux-a96aed0636d49f39e4c9eb85ef7c8630e12e3421.zip | |
Merge tag 'renesas-r9a08g045-dt-binding-defs-tag' into renesas-clk-for-v6.7
Renesas RZ/G3S DT Binding Definitions
Clock definitions for the Renesas RZ/G3S (R9A08G045) SoC, shared by
driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions