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| author |   Pan Wen <wenpan@hisilicon.com> | 2016-11-14 10:49:54 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2016-11-14 12:04:39 -0800 |
| commit | c80dfd9bf54e178207b7bd124b0dd5e2453b87fe (patch) | |
| tree | ad4400fa554448fdb4477ce0526a434d4bd0962a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: hisilicon: add CRG driver for Hi3798CV200 SoC (diff) | |
| download | wireguard-linux-c80dfd9bf54e178207b7bd124b0dd5e2453b87fe.tar.xz wireguard-linux-c80dfd9bf54e178207b7bd124b0dd5e2453b87fe.zip | |
clk: hisilicon: add CRG driver for Hi3516CV300 SoC
Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.
Signed-off-by: Pan Wen <wenpan@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions