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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-04-03 11:45:41 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-04-03 06:32:33 -0400 |
| commit | d13d4e063d4a08eb1686e890e9183dde709871bf (patch) | |
| tree | 92d0e0dde6aa244d27f9387efd34a61a457c87bd /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: r7s72100: fix ethernet clock parent (diff) | |
| download | wireguard-linux-d13d4e063d4a08eb1686e890e9183dde709871bf.tar.xz wireguard-linux-d13d4e063d4a08eb1686e890e9183dde709871bf.zip | |
ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks
The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: bcde372254386872 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions