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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2020-05-03 22:46:50 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2020-05-05 09:44:49 +0200 |
| commit | eb4cdda7a30b3f9894fd5a58e0201fa57861183f (patch) | |
| tree | 1956fdcde58cc084763488b39deb616f5a49c467 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge tag 'renesas-r8a7742-dt-binding-defs-tag' into renesas-arm-dt-for-v5.8 (diff) | |
| download | wireguard-linux-eb4cdda7a30b3f9894fd5a58e0201fa57861183f.tar.xz wireguard-linux-eb4cdda7a30b3f9894fd5a58e0201fa57861183f.zip | |
ARM: dts: r8a7742: Initial SoC device tree
The initial R8A7742 SoC device tree including CPU[0-8], PMU, PFC,
CPG, RST, SYSC, ICRAM[0-2], SCIFA2, MMC1, DMAC[0-1], GIC, PRR, timer
and the required clock descriptions.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588542414-14826-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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