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| author |   Joseph Lo <josephl@nvidia.com> | 2019-01-04 11:07:00 +0800 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2019-02-07 19:03:56 +0100 |
| commit | f9c8bcc00290e7b46188fc9e87aaec0ebeba0286 (patch) | |
| tree | 772c633e7e52cd986856ae4614f331a51c2dde50 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: tegra: Enable DFLL clock on Jetson TX1 (diff) | |
| download | wireguard-linux-f9c8bcc00290e7b46188fc9e87aaec0ebeba0286.tar.xz wireguard-linux-f9c8bcc00290e7b46188fc9e87aaec0ebeba0286.zip | |
arm64: tegra: Add CPU power rail regulator on Smaug
Add CPU power rail regulator for Smaug board.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions