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| author |   Duy Nguyen <duy.nguyen.rh@renesas.com> | 2024-02-01 15:19:19 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-22 11:03:32 +0100 |
| commit | 4c1fd23a220dccaf4b8192d863997213af6e2c31 (patch) | |
| tree | 68d950bde30ca80f8389a03d6cbca7411e962ca5 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | arm64: dts: renesas: r8a779h0: Add CPUIdle support (diff) | |
| download | wireguard-linux-4c1fd23a220dccaf4b8192d863997213af6e2c31.tar.xz wireguard-linux-4c1fd23a220dccaf4b8192d863997213af6e2c31.zip | |
arm64: dts: renesas: r8a779h0: Add CPU core clocks
Describe the clocks for the four Cortex-A76 CPU cores.
CA76 CPU cores 0,1,2,3 are clocked by ZC0,ZC1,ZC2,ZC3.
Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c64cf6ca1590fa1a36b90a18fd70c831d5b8318e.1706796979.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions