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| author |   Aric Cyr <Aric.Cyr@amd.com> | 2022-11-21 00:12:38 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-11-29 11:03:38 -0500 |
| commit | 68a60f6bab476970e73690649b5c4b60e0249b65 (patch) | |
| tree | cf779c17c317c9ea82e34eceb39096687ae3a2df /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | drm/amd/display: Use the largest vready_offset in pipe group (diff) | |
| download | wireguard-linux-68a60f6bab476970e73690649b5c4b60e0249b65.tar.xz wireguard-linux-68a60f6bab476970e73690649b5c4b60e0249b65.zip | |
drm/amd/display: 3.2.214
This version brings along following fixes:
-Program output transfer function when required
-Fix arthmetic errror in MALL size caluclations for subvp
-DCC Meta pitch used for MALL allocation
-Debugfs entry to tell if connector is DPIA link
-Use largest vready_offset in pipe group
-Fixes race condition in DPIA Aux transfer
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions