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| author |   Alain Volmat <avolmat@me.com> | 2021-03-31 22:42:24 +0200 |
|---|---|---|
| committer |   Patrice Chotard <patrice.chotard@foss.st.com> | 2021-08-06 09:30:02 +0200 |
| commit | a1b68d6b02b6b3d92dc9093d3f56688bc463bb73 (patch) | |
| tree | d847344f13a6c49b3cba2b9c5c9d53c0d53a8dbf /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | ARM: dts: sti: update clkgen-fsyn entries in stih410-clock (diff) | |
| download | wireguard-linux-a1b68d6b02b6b3d92dc9093d3f56688bc463bb73.tar.xz wireguard-linux-a1b68d6b02b6b3d92dc9093d3f56688bc463bb73.zip | |
ARM: dts: sti: update clkgen-fsyn entries in stih418-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions