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| author |   Thierry Reding <treding@nvidia.com> | 2023-07-26 20:25:32 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2023-07-27 16:48:25 +0200 |
| commit | d7fb6468ec9f18db52ef3c84eb44a9025021c830 (patch) | |
| tree | 2ca8e1516986a78421601590eb5356f97fcbda31 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | arm64: tegra: Remove {clock,reset}-names from VIC powergate (diff) | |
| download | wireguard-linux-d7fb6468ec9f18db52ef3c84eb44a9025021c830.tar.xz wireguard-linux-d7fb6468ec9f18db52ef3c84eb44a9025021c830.zip | |
arm64: tegra: Add blank lines for better readability
Add a few blank lines to visually separate blocks in the Jetson AGX Orin
device tree.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions