diff options
| author |   Zhen Lei <thunder.leizhen@huawei.com> | 2021-05-21 17:20:42 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2021-06-12 16:17:02 +0800 |
| commit | ce87d936889bdb183590647b9827bb2ae7f674c7 (patch) | |
| tree | e77672b818502c172902e0917c5b6d9bf3f2a0aa /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | arm64: dts: imx8: conn: fix enet clock setting (diff) | |
| download | wireguard-linux-ce87d936889bdb183590647b9827bb2ae7f674c7.tar.xz wireguard-linux-ce87d936889bdb183590647b9827bb2ae7f674c7.zip | |
arm64: dts: freescale: Separate each group of data in the property 'reg'
Do not write the 'reg' of multiple groups of data into a uint32 array,
use <> to separate them. Otherwise, the errors similar to the following
will be reported by reg.yaml.
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dt.yaml:
soc: pcie@3400000:reg:0: \
[0, 54525952, 0, 1048576, 64, 0, 0, 8192] is too long
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions