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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-26 12:37:51 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-26 12:37:51 +0200 |
| commit | f5684bde0375f4feb2a9ed1c146df29437652e70 (patch) | |
| tree | 5de0ff7d5fb8c5d92122091f96dfd518c9f256ce /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: renesas: r9a07g044: Add MTU3a clock and reset entry (diff) | |
| parent | clk: renesas: r8a779g0: Fix HSCIF parent clocks (diff) | |
| download | wireguard-linux-f5684bde0375f4feb2a9ed1c146df29437652e70.tar.xz wireguard-linux-f5684bde0375f4feb2a9ed1c146df29437652e70.zip | |
Merge tag 'renesas-clk-fixes-for-v6.1-tag1'
clk: renesas: Fixes for v6.1
- Correct the parent clocks for the High Speed Serial Communication
Interfaces with FIFO (HSCIF) modules on the R-Car V4H SoC.
Note that HSCIF0 is used for the serial console on the White-Hawk
development board.
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions