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author | 2021-02-09 16:03:39 -0800 | |
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committer | 2021-02-09 16:03:39 -0800 | |
commit | e3272b0bc9d6f4cb0032e422c5bd4f93f994a913 (patch) | |
tree | de1c67050817de94ecabd93b954882423850aee5 /tools/perf/scripts/python/stackcollapse.py | |
parent | Linux 5.11-rc1 (diff) | |
parent | clk: meson: axg: Remove MIPI enable clock gate (diff) | |
download | wireguard-linux-e3272b0bc9d6f4cb0032e422c5bd4f93f994a913.tar.xz wireguard-linux-e3272b0bc9d6f4cb0032e422c5bd4f93f994a913.zip |
Merge tag 'clk-meson-v5.12-1-fixed' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet:
- pll driver fixup
- meson8b clock controller dt support clean up
- remove mipi clk from the axg clock controller
* tag 'clk-meson-v5.12-1-fixed' of https://github.com/BayLibre/clk-meson:
clk: meson: axg: Remove MIPI enable clock gate
clk: meson-axg: remove CLKID_MIPI_ENABLE
dt-bindings: clock: meson8b: remove non-existing clock macros
clk: meson: meson8b: remove compatibility code for old .dtbs
clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()
clk: meson: clk-pll: make "ret" a signed integer
clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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