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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-06-25 15:17:05 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-02 20:51:46 +0200 |
| commit | 0475a478d0a88c7ec31763697eb01b25957bece3 (patch) | |
| tree | fff8ab964c58106e547dd3a799524094fca22fc1 /tools/perf/scripts/python | |
| parent | clk: renesas: r9a09g077: Add PLL2 and SDHI clock support (diff) | |
| download | wireguard-linux-0475a478d0a88c7ec31763697eb01b25957bece3.tar.xz wireguard-linux-0475a478d0a88c7ec31763697eb01b25957bece3.zip | |
clk: renesas: r9a09g077: Add RIIC module clocks
Add RIIC module clocks for: iic0, iic1, and iic2.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250625141705.151383-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions