diff options
| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-06-25 15:17:04 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-02 20:51:43 +0200 |
| commit | 09d50e09fab65f42d4656e9b01f225db7d311348 (patch) | |
| tree | 77d455f2a5354038867c7c5e980029879f0c1732 /tools/perf/scripts/python | |
| parent | Merge tag 'renesas-r9a09g087-dt-binding-defs-tag2' into renesas-clk-for-v6.17 (diff) | |
| download | wireguard-linux-09d50e09fab65f42d4656e9b01f225db7d311348.tar.xz wireguard-linux-09d50e09fab65f42d4656e9b01f225db7d311348.zip | |
clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
Add support for PLL2 to the R9A09G077 (RZ/T2H) clock definitions and
register it as the source for the high-speed SDHI clock (SDHI_CLKHS)
operating at 800MHz.
Also add fixed-factor clock PCLKAM derived from CLK_PLL4D1, and define
module clocks for SDHI0 and SDHI1, both of which use PCLKAM as their
clock source.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250625141705.151383-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions