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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-02 20:49:48 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-02 20:49:48 +0200 |
| commit | 8f9ad7670b6e4b434ac65449ac3e31aada1bef4c (patch) | |
| tree | 82c745f6c6c4d5f45e4b9e7fe157fdae3b96d1b5 /tools/perf/scripts/python | |
| parent | clk: renesas: rzv2h: Drop redundant base pointer from pll_clk (diff) | |
| parent | dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID (diff) | |
| download | wireguard-linux-8f9ad7670b6e4b434ac65449ac3e31aada1bef4c.tar.xz wireguard-linux-8f9ad7670b6e4b434ac65449ac3e31aada1bef4c.zip | |
Merge tag 'renesas-r9a09g087-dt-binding-defs-tag2' into renesas-clk-for-v6.17
Renesas RZ/T2H and RZ/N2H SDHI Clock DT Binding Definitions
SDHI clock DT binding definitions for the Renesas RZ/T2H (R9A09G077) and
RZ/N2H (R9A09G087) SoCs, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions