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| author |   Anup Patel <apatel@ventanamicro.com> | 2022-07-18 14:15:53 +0530 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-09-23 03:56:00 -0700 |
| commit | cfadbb9df8c4dc917787da4458327e5ec14743d4 (patch) | |
| tree | a2ab5b7d7fe3d366bcd221e8fa6c89e77ad77dfe /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | perf: RISC-V: throttle perf events (diff) | |
| download | wireguard-linux-cfadbb9df8c4dc917787da4458327e5ec14743d4.tar.xz wireguard-linux-cfadbb9df8c4dc917787da4458327e5ec14743d4.zip | |
cpuidle: riscv-sbi: Fix CPU_PM_CPU_IDLE_ENTER_xyz() macro usage
Currently, we are using CPU_PM_CPU_IDLE_ENTER_PARAM() for all SBI HSM
suspend types so retentive suspend types are also treated non-retentive
and kernel will do redundant additional work for these states.
The BIT[31] of SBI HSM suspend types allows us to differentiate between
retentive and non-retentive suspend types so we should use this BIT
to call appropriate CPU_PM_CPU_IDLE_ENTER_xyz() macro.
Fixes: 6abf32f1d9c5 ("cpuidle: Add RISC-V SBI CPU idle driver")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20220718084553.2056169-1-apatel@ventanamicro.com/
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions