diff options
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 91 | ||||
| -rw-r--r-- | drivers/clk/tegra/clk-tegra114.c | 122 | ||||
| -rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 93 | ||||
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 150 | ||||
| -rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 227 |
5 files changed, 379 insertions, 304 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c645a899deba..b8b3fc6dc39b 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -435,6 +435,7 @@ static int _get_table_rate(struct clk_hw *hw, { struct tegra_clk_pll *pll = to_clk_pll(hw); struct tegra_clk_pll_freq_table *sel; + int p; for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) if (sel->input_rate == parent_rate && @@ -444,11 +445,19 @@ static int _get_table_rate(struct clk_hw *hw, if (sel->input_rate == 0) return -EINVAL; + if (pll->params->pdiv_tohw) { + p = _p_div_to_hw(hw, sel->p); + if (p < 0) + return p; + } else { + p = ilog2(sel->p); + } + cfg->input_rate = sel->input_rate; cfg->output_rate = sel->output_rate; cfg->m = sel->m; cfg->n = sel->n; - cfg->p = sel->p; + cfg->p = p; cfg->cpcon = sel->cpcon; cfg->sdm_data = sel->sdm_data; @@ -908,10 +917,6 @@ const struct clk_ops tegra_clk_plle_ops = { .enable = clk_plle_enable, }; -#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ - defined(CONFIG_ARCH_TEGRA_124_SOC) || \ - defined(CONFIG_ARCH_TEGRA_132_SOC) - static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, unsigned long parent_rate) { @@ -930,6 +935,39 @@ static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, return 1; } +static int _calc_dynamic_ramp_rate(struct clk_hw *hw, + struct tegra_clk_pll_freq_table *cfg, + unsigned long rate, unsigned long parent_rate) +{ + struct tegra_clk_pll *pll = to_clk_pll(hw); + unsigned int p; + int p_div; + + if (!rate) + return -EINVAL; + + p = DIV_ROUND_UP(pll->params->vco_min, rate); + cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); + cfg->output_rate = rate * p; + cfg->n = cfg->output_rate * cfg->m / parent_rate; + cfg->input_rate = parent_rate; + + p_div = _p_div_to_hw(hw, p); + if (p_div < 0) + return p_div; + + cfg->p = p_div; + + if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) + return -EINVAL; + + return 0; +} + +#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ + defined(CONFIG_ARCH_TEGRA_124_SOC) || \ + defined(CONFIG_ARCH_TEGRA_132_SOC) + u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate) { struct tegra_clk_pll *pll = to_clk_pll(hw); @@ -979,40 +1017,12 @@ static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, return 0; } -static int _calc_dynamic_ramp_rate(struct clk_hw *hw, - struct tegra_clk_pll_freq_table *cfg, - unsigned long rate, unsigned long parent_rate) -{ - struct tegra_clk_pll *pll = to_clk_pll(hw); - unsigned int p; - int p_div; - - if (!rate) - return -EINVAL; - - p = DIV_ROUND_UP(pll->params->vco_min, rate); - cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); - cfg->output_rate = rate * p; - cfg->n = cfg->output_rate * cfg->m / parent_rate; - - p_div = _p_div_to_hw(hw, p); - if (p_div < 0) - return p_div; - - cfg->p = p_div; - - if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) - return -EINVAL; - - return 0; -} - static int _pll_ramp_calc_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) { struct tegra_clk_pll *pll = to_clk_pll(hw); - int err = 0, p_div; + int err = 0; err = _get_table_rate(hw, cfg, rate, parent_rate); if (err < 0) @@ -1023,11 +1033,6 @@ static int _pll_ramp_calc_pll(struct clk_hw *hw, err = -EINVAL; goto out; } - p_div = _p_div_to_hw(hw, cfg->p); - if (p_div < 0) - return p_div; - else - cfg->p = p_div; } if (cfg->p > pll->params->max_p) @@ -1512,8 +1517,12 @@ static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, init.num_parents = (parent_name ? 1 : 0); /* Default to _calc_rate if unspecified */ - if (!pll->params->calc_rate) - pll->params->calc_rate = _calc_rate; + if (!pll->params->calc_rate) { + if (pll->params->flags & TEGRA_PLLM) + pll->params->calc_rate = _calc_dynamic_ramp_rate; + else + pll->params->calc_rate = _calc_rate; + } /* Data in .init is copied by clk_register(), so stack variable OK */ pll->hw.init = &init; diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 0b942e0cacc2..9411a1577d85 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -202,12 +202,12 @@ static const struct pdiv_map pllxc_p[] = { }; static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { - { 12000000, 624000000, 104, 0, 2, 0 }, - { 12000000, 600000000, 100, 0, 2, 0 }, - { 13000000, 600000000, 92, 0, 2, 0 }, /* actual: 598.0 MHz */ - { 16800000, 600000000, 71, 0, 2, 0 }, /* actual: 596.4 MHz */ - { 19200000, 600000000, 62, 0, 2, 0 }, /* actual: 595.2 MHz */ - { 26000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ + { 12000000, 624000000, 104, 1, 2, 0 }, + { 12000000, 600000000, 100, 1, 2, 0 }, + { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ + { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ + { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ + { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ { 0, 0, 0, 0, 0, 0 }, }; @@ -254,11 +254,11 @@ static const struct pdiv_map pllc_p[] = { }; static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { - { 12000000, 600000000, 100, 0, 2, 0 }, - { 13000000, 600000000, 92, 0, 2, 0 }, /* actual: 598.0 MHz */ - { 16800000, 600000000, 71, 0, 2, 0 }, /* actual: 596.4 MHz */ - { 19200000, 600000000, 62, 0, 2, 0 }, /* actual: 595.2 MHz */ - { 26000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ + { 12000000, 600000000, 100, 1, 2, 0 }, + { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ + { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ + { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ + { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ { 0, 0, 0, 0, 0, 0 }, }; @@ -325,11 +325,11 @@ static const struct pdiv_map pllm_p[] = { }; static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { - { 12000000, 800000000, 66, 0, 1, 0 }, /* actual: 792.0 MHz */ - { 13000000, 800000000, 61, 0, 1, 0 }, /* actual: 793.0 MHz */ - { 16800000, 800000000, 47, 0, 1, 0 }, /* actual: 789.6 MHz */ - { 19200000, 800000000, 41, 0, 1, 0 }, /* actual: 787.2 MHz */ - { 26000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */ + { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */ + { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */ + { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */ + { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */ + { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */ { 0, 0, 0, 0, 0, 0 }, }; @@ -364,11 +364,11 @@ static struct div_nmp pllp_nmp = { }; static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { - { 12000000, 216000000, 432, 12, 1, 8 }, - { 13000000, 216000000, 432, 13, 1, 8 }, - { 16800000, 216000000, 360, 14, 1, 8 }, - { 19200000, 216000000, 360, 16, 1, 8 }, - { 26000000, 216000000, 432, 26, 1, 8 }, + { 12000000, 216000000, 432, 12, 2, 8 }, + { 13000000, 216000000, 432, 13, 2, 8 }, + { 16800000, 216000000, 360, 14, 2, 8 }, + { 19200000, 216000000, 360, 16, 2, 8 }, + { 26000000, 216000000, 432, 26, 2, 8 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -392,12 +392,12 @@ static struct tegra_clk_pll_params pll_p_params = { }; static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { - { 9600000, 282240000, 147, 5, 0, 4 }, - { 9600000, 368640000, 192, 5, 0, 4 }, - { 9600000, 240000000, 200, 8, 0, 8 }, - { 28800000, 282240000, 245, 25, 0, 8 }, - { 28800000, 368640000, 320, 25, 0, 8 }, - { 28800000, 240000000, 200, 24, 0, 8 }, + { 9600000, 282240000, 147, 5, 1, 4 }, + { 9600000, 368640000, 192, 5, 1, 4 }, + { 9600000, 240000000, 200, 8, 1, 8 }, + { 28800000, 282240000, 245, 25, 1, 8 }, + { 28800000, 368640000, 320, 25, 1, 8 }, + { 28800000, 240000000, 200, 24, 1, 8 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -421,20 +421,20 @@ static struct tegra_clk_pll_params pll_a_params = { }; static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { - { 12000000, 216000000, 864, 12, 2, 12 }, - { 13000000, 216000000, 864, 13, 2, 12 }, - { 16800000, 216000000, 720, 14, 2, 12 }, - { 19200000, 216000000, 720, 16, 2, 12 }, - { 26000000, 216000000, 864, 26, 2, 12 }, - { 12000000, 594000000, 594, 12, 0, 12 }, - { 13000000, 594000000, 594, 13, 0, 12 }, - { 16800000, 594000000, 495, 14, 0, 12 }, - { 19200000, 594000000, 495, 16, 0, 12 }, - { 26000000, 594000000, 594, 26, 0, 12 }, - { 12000000, 1000000000, 1000, 12, 0, 12 }, - { 13000000, 1000000000, 1000, 13, 0, 12 }, - { 19200000, 1000000000, 625, 12, 0, 12 }, - { 26000000, 1000000000, 1000, 26, 0, 12 }, + { 12000000, 216000000, 864, 12, 4, 12 }, + { 13000000, 216000000, 864, 13, 4, 12 }, + { 16800000, 216000000, 720, 14, 4, 12 }, + { 19200000, 216000000, 720, 16, 4, 12 }, + { 26000000, 216000000, 864, 26, 4, 12 }, + { 12000000, 594000000, 594, 12, 1, 12 }, + { 13000000, 594000000, 594, 13, 1, 12 }, + { 16800000, 594000000, 495, 14, 1, 12 }, + { 19200000, 594000000, 495, 16, 1, 12 }, + { 26000000, 594000000, 594, 26, 1, 12 }, + { 12000000, 1000000000, 1000, 12, 1, 12 }, + { 13000000, 1000000000, 1000, 13, 1, 12 }, + { 19200000, 1000000000, 625, 12, 1, 12 }, + { 26000000, 1000000000, 1000, 26, 1, 12 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -490,11 +490,11 @@ static struct div_nmp pllu_nmp = { }; static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { - { 12000000, 480000000, 960, 12, 0, 12 }, - { 13000000, 480000000, 960, 13, 0, 12 }, - { 16800000, 480000000, 400, 7, 0, 5 }, - { 19200000, 480000000, 200, 4, 0, 3 }, - { 26000000, 480000000, 960, 26, 0, 12 }, + { 12000000, 480000000, 960, 12, 2, 12 }, + { 13000000, 480000000, 960, 13, 2, 12 }, + { 16800000, 480000000, 400, 7, 2, 5 }, + { 19200000, 480000000, 200, 4, 2, 3 }, + { 26000000, 480000000, 960, 26, 2, 12 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -519,11 +519,11 @@ static struct tegra_clk_pll_params pll_u_params = { static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { /* 1 GHz */ - { 12000000, 1000000000, 83, 0, 1, 0 }, /* actual: 996.0 MHz */ - { 13000000, 1000000000, 76, 0, 1, 0 }, /* actual: 988.0 MHz */ - { 16800000, 1000000000, 59, 0, 1, 0 }, /* actual: 991.2 MHz */ - { 19200000, 1000000000, 52, 0, 1, 0 }, /* actual: 998.4 MHz */ - { 26000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */ + { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */ + { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */ + { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */ + { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */ + { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */ { 0, 0, 0, 0, 0, 0 }, }; @@ -559,6 +559,25 @@ static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { { 0, 0, 0, 0, 0, 0 }, }; +static const struct pdiv_map plle_p[] = { + { .pdiv = 1, .hw_val = 0 }, + { .pdiv = 2, .hw_val = 1 }, + { .pdiv = 3, .hw_val = 2 }, + { .pdiv = 4, .hw_val = 3 }, + { .pdiv = 5, .hw_val = 4 }, + { .pdiv = 6, .hw_val = 5 }, + { .pdiv = 8, .hw_val = 6 }, + { .pdiv = 10, .hw_val = 7 }, + { .pdiv = 12, .hw_val = 8 }, + { .pdiv = 16, .hw_val = 9 }, + { .pdiv = 12, .hw_val = 10 }, + { .pdiv = 16, .hw_val = 11 }, + { .pdiv = 20, .hw_val = 12 }, + { .pdiv = 24, .hw_val = 13 }, + { .pdiv = 32, .hw_val = 14 }, + { .pdiv = 0, .hw_val = 0 } +}; + static struct div_nmp plle_nmp = { .divm_shift = 0, .divm_width = 8, @@ -581,6 +600,7 @@ static struct tegra_clk_pll_params pll_e_params = { .lock_mask = PLLE_MISC_LOCK, .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, .lock_delay = 300, + .pdiv_tohw = plle_p, .div_nmp = &plle_nmp, .freq_table = pll_e_freq_table, .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE, diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 3c93dbf4b9bd..1627258292d2 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -189,11 +189,11 @@ static const struct pdiv_map pllxc_p[] = { static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { /* 1 GHz */ - { 12000000, 1000000000, 83, 0, 1, 0 }, /* actual: 996.0 MHz */ - { 13000000, 1000000000, 76, 0, 1, 0 }, /* actual: 988.0 MHz */ - { 16800000, 1000000000, 59, 0, 1, 0 }, /* actual: 991.2 MHz */ - { 19200000, 1000000000, 52, 0, 1, 0 }, /* actual: 998.4 MHz */ - { 26000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */ + { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */ + { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */ + { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */ + { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */ + { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */ { 0, 0, 0, 0, 0, 0 }, }; @@ -358,11 +358,11 @@ static const struct pdiv_map pll12g_ssd_esd_p[] = { }; static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = { - { 12000000, 600000000, 100, 1, 1, 0 }, - { 13000000, 600000000, 92, 1, 1, 0 }, /* actual: 598.0 MHz */ - { 16800000, 600000000, 71, 1, 1, 0 }, /* actual: 596.4 MHz */ - { 19200000, 600000000, 62, 1, 1, 0 }, /* actual: 595.2 MHz */ - { 26000000, 600000000, 92, 2, 1, 0 }, /* actual: 598.0 MHz */ + { 12000000, 600000000, 100, 1, 2, 0 }, + { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ + { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ + { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ + { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ { 0, 0, 0, 0, 0, 0 }, }; @@ -390,9 +390,22 @@ static struct tegra_clk_pll_params pll_c4_params = { }; static const struct pdiv_map pllm_p[] = { - { .pdiv = 1, .hw_val = 0 }, - { .pdiv = 2, .hw_val = 1 }, - { .pdiv = 0, .hw_val = 0 }, + { .pdiv = 1, .hw_val = 0 }, + { .pdiv = 2, .hw_val = 1 }, + { .pdiv = 3, .hw_val = 2 }, + { .pdiv = 4, .hw_val = 3 }, + { .pdiv = 5, .hw_val = 4 }, + { .pdiv = 6, .hw_val = 5 }, + { .pdiv = 8, .hw_val = 6 }, + { .pdiv = 10, .hw_val = 7 }, + { .pdiv = 12, .hw_val = 8 }, + { .pdiv = 16, .hw_val = 9 }, + { .pdiv = 12, .hw_val = 10 }, + { .pdiv = 16, .hw_val = 11 }, + { .pdiv = 20, .hw_val = 12 }, + { .pdiv = 24, .hw_val = 13 }, + { .pdiv = 32, .hw_val = 14 }, + { .pdiv = 0, .hw_val = 0 }, }; static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { @@ -428,7 +441,7 @@ static struct tegra_clk_pll_params pll_m_params = { .lock_mask = PLL_BASE_LOCK, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_delay = 300, - .max_p = 2, + .max_p = 5, .pdiv_tohw = pllm_p, .div_nmp = &pllm_nmp, .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, @@ -446,6 +459,25 @@ static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { { 0, 0, 0, 0, 0, 0 }, }; +static const struct pdiv_map plle_p[] = { + { .pdiv = 1, .hw_val = 0 }, + { .pdiv = 2, .hw_val = 1 }, + { .pdiv = 3, .hw_val = 2 }, + { .pdiv = 4, .hw_val = 3 }, + { .pdiv = 5, .hw_val = 4 }, + { .pdiv = 6, .hw_val = 5 }, + { .pdiv = 8, .hw_val = 6 }, + { .pdiv = 10, .hw_val = 7 }, + { .pdiv = 12, .hw_val = 8 }, + { .pdiv = 16, .hw_val = 9 }, + { .pdiv = 12, .hw_val = 10 }, + { .pdiv = 16, .hw_val = 11 }, + { .pdiv = 20, .hw_val = 12 }, + { .pdiv = 24, .hw_val = 13 }, + { .pdiv = 32, .hw_val = 14 }, + { .pdiv = 1, .hw_val = 0 }, +}; + static struct div_nmp plle_nmp = { .divm_shift = 0, .divm_width = 8, @@ -468,6 +500,7 @@ static struct tegra_clk_pll_params pll_e_params = { .lock_mask = PLLE_MISC_LOCK, .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, .lock_delay = 300, + .pdiv_tohw = plle_p, .div_nmp = &plle_nmp, .freq_table = pll_e_freq_table, .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE, @@ -522,11 +555,11 @@ static struct div_nmp pllp_nmp = { }; static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { - { 12000000, 408000000, 408, 12, 0, 8 }, - { 13000000, 408000000, 408, 13, 0, 8 }, - { 16800000, 408000000, 340, 14, 0, 8 }, - { 19200000, 408000000, 340, 16, 0, 8 }, - { 26000000, 408000000, 408, 26, 0, 8 }, + { 12000000, 408000000, 408, 12, 1, 8 }, + { 13000000, 408000000, 408, 13, 1, 8 }, + { 16800000, 408000000, 340, 14, 1, 8 }, + { 19200000, 408000000, 340, 16, 1, 8 }, + { 26000000, 408000000, 408, 26, 1, 8 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -550,12 +583,12 @@ static struct tegra_clk_pll_params pll_p_params = { }; static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { - { 9600000, 282240000, 147, 5, 0, 4 }, - { 9600000, 368640000, 192, 5, 0, 4 }, - { 9600000, 240000000, 200, 8, 0, 8 }, - { 28800000, 282240000, 245, 25, 0, 8 }, - { 28800000, 368640000, 320, 25, 0, 8 }, - { 28800000, 240000000, 200, 24, 0, 8 }, + { 9600000, 282240000, 147, 5, 1, 4 }, + { 9600000, 368640000, 192, 5, 1, 4 }, + { 9600000, 240000000, 200, 8, 1, 8 }, + { 28800000, 282240000, 245, 25, 1, 8 }, + { 28800000, 368640000, 320, 25, 1, 8 }, + { 28800000, 240000000, 200, 24, 1, 8 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -656,11 +689,11 @@ static struct tegra_clk_pll_params tegra124_pll_d2_params = { }; static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { - { 12000000, 600000000, 100, 1, 1, 0 }, - { 13000000, 600000000, 92, 1, 1, 0 }, /* actual: 598.0 MHz */ - { 16800000, 600000000, 71, 1, 1, 0 }, /* actual: 596.4 MHz */ - { 19200000, 600000000, 62, 1, 1, 0 }, /* actual: 595.2 MHz */ - { 26000000, 600000000, 92, 2, 1, 0 }, /* actual: 598.0 MHz */ + { 12000000, 600000000, 100, 1, 2, 0 }, + { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ + { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ + { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ + { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ { 0, 0, 0, 0, 0, 0 }, }; diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index b49d94bc0b8f..7a48e986c4c9 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -166,114 +166,119 @@ static DEFINE_SPINLOCK(emc_lock); static struct clk **clks; static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { - { 12000000, 600000000, 600, 12, 0, 8 }, - { 13000000, 600000000, 600, 13, 0, 8 }, - { 19200000, 600000000, 500, 16, 0, 6 }, - { 26000000, 600000000, 600, 26, 0, 8 }, + { 12000000, 600000000, 600, 12, 1, 8 }, + { 13000000, 600000000, 600, 13, 1, 8 }, + { 19200000, 600000000, 500, 16, 1, 6 }, + { 26000000, 600000000, 600, 26, 1, 8 }, { 0, 0, 0, 0, 0, 0 }, }; static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { - { 12000000, 666000000, 666, 12, 0, 8 }, - { 13000000, 666000000, 666, 13, 0, 8 }, - { 19200000, 666000000, 555, 16, 0, 8 }, - { 26000000, 666000000, 666, 26, 0, 8 }, - { 12000000, 600000000, 600, 12, 0, 8 }, - { 13000000, 600000000, 600, 13, 0, 8 }, - { 19200000, 600000000, 375, 12, 0, 6 }, - { 26000000, 600000000, 600, 26, 0, 8 }, + { 12000000, 666000000, 666, 12, 1, 8 }, + { 13000000, 666000000, 666, 13, 1, 8 }, + { 19200000, 666000000, 555, 16, 1, 8 }, + { 26000000, 666000000, 666, 26, 1, 8 }, + { 12000000, 600000000, 600, 12, 1, 8 }, + { 13000000, 600000000, 600, 13, 1, 8 }, + { 19200000, 600000000, 375, 12, 1, 6 }, + { 26000000, 600000000, 600, 26, 1, 8 }, { 0, 0, 0, 0, 0, 0 }, }; static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { - { 12000000, 216000000, 432, 12, 1, 8 }, - { 13000000, 216000000, 432, 13, 1, 8 }, - { 19200000, 216000000, 90, 4, 1, 1 }, - { 26000000, 216000000, 432, 26, 1, 8 }, - { 12000000, 432000000, 432, 12, 0, 8 }, - { 13000000, 432000000, 432, 13, 0, 8 }, - { 19200000, 432000000, 90, 4, 0, 1 }, - { 26000000, 432000000, 432, 26, 0, 8 }, + { 12000000, 216000000, 432, 12, 2, 8 }, + { 13000000, 216000000, 432, 13, 2, 8 }, + { 19200000, 216000000, 90, 4, 2, 1 }, + { 26000000, 216000000, 432, 26, 2, 8 }, + { 12000000, 432000000, 432, 12, 1, 8 }, + { 13000000, 432000000, 432, 13, 1, 8 }, + { 19200000, 432000000, 90, 4, 1, 1 }, + { 26000000, 432000000, 432, 26, 1, 8 }, { 0, 0, 0, 0, 0, 0 }, }; static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { - { 28800000, 56448000, 49, 25, 0, 1 }, - { 28800000, 73728000, 64, 25, 0, 1 }, - { 28800000, 24000000, 5, 6, 0, 1 }, + { 28800000, 56448000, 49, 25, 1, 1 }, + { 28800000, 73728000, 64, 25, 1, 1 }, + { 28800000, 24000000, 5, 6, 1, 1 }, { 0, 0, 0, 0, 0, 0 }, }; static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { - { 12000000, 216000000, 216, 12, 0, 4 }, - { 13000000, 216000000, 216, 13, 0, 4 }, - { 19200000, 216000000, 135, 12, 0, 3 }, - { 26000000, 216000000, 216, 26, 0, 4 }, - { 12000000, 594000000, 594, 12, 0, 8 }, - { 13000000, 594000000, 594, 13, 0, 8 }, - { 19200000, 594000000, 495, 16, 0, 8 }, - { 26000000, 594000000, 594, 26, 0, 8 }, - { 12000000, 1000000000, 1000, 12, 0, 12 }, - { 13000000, 1000000000, 1000, 13, 0, 12 }, - { 19200000, 1000000000, 625, 12, 0, 8 }, - { 26000000, 1000000000, 1000, 26, 0, 12 }, + { 12000000, 216000000, 216, 12, 1, 4 }, + { 13000000, 216000000, 216, 13, 1, 4 }, + { 19200000, 216000000, 135, 12, 1, 3 }, + { 26000000, 216000000, 216, 26, 1, 4 }, + { 12000000, 594000000, 594, 12, 1, 8 }, + { 13000000, 594000000, 594, 13, 1, 8 }, + { 19200000, 594000000, 495, 16, 1, 8 }, + { 26000000, 594000000, 594, 26, 1, 8 }, + { 12000000, 1000000000, 1000, 12, 1, 12 }, + { 13000000, 1000000000, 1000, 13, 1, 12 }, + { 19200000, 1000000000, 625, 12, 1, 8 }, + { 26000000, 1000000000, 1000, 26, 1, 12 }, { 0, 0, 0, 0, 0, 0 }, }; static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { - { 12000000, 480000000, 960, 12, 0, 0 }, - { 13000000, 480000000, 960, 13, 0, 0 }, - { 19200000, 480000000, 200, 4, 0, 0 }, - { 26000000, 480000000, 960, 26, 0, 0 }, + { 12000000, 480000000, 960, 12, 1, 0 }, + { 13000000, 480000000, 960, 13, 1, 0 }, + { 19200000, 480000000, 200, 4, 1, 0 }, + { 26000000, 480000000, 960, 26, 1, 0 }, { 0, 0, 0, 0, 0, 0 }, }; static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { /* 1 GHz */ - { 12000000, 1000000000, 1000, 12, 0, 12 }, - { 13000000, 1000000000, 1000, 13, 0, 12 }, - { 19200000, 1000000000, 625, 12, 0, 8 }, - { 26000000, 1000000000, 1000, 26, 0, 12 }, + { 12000000, 1000000000, 1000, 12, 1, 12 }, + { 13000000, 1000000000, 1000, 13, 1, 12 }, + { 19200000, 1000000000, 625, 12, 1, 8 }, + { 26000000, 1000000000, 1000, 26, 1, 12 }, /* 912 MHz */ - { 12000000, 912000000, 912, 12, 0, 12 }, - { 13000000, 912000000, 912, 13, 0, 12 }, - { 19200000, 912000000, 760, 16, 0, 8 }, - { 26000000, 912000000, 912, 26, 0, 12 }, + { 12000000, 912000000, 912, 12, 1, 12 }, + { 13000000, 912000000, 912, 13, 1, 12 }, + { 19200000, 912000000, 760, 16, 1, 8 }, + { 26000000, 912000000, 912, 26, 1, 12 }, /* 816 MHz */ - { 12000000, 816000000, 816, 12, 0, 12 }, - { 13000000, 816000000, 816, 13, 0, 12 }, - { 19200000, 816000000, 680, 16, 0, 8 }, - { 26000000, 816000000, 816, 26, 0, 12 }, + { 12000000, 816000000, 816, 12, 1, 12 }, + { 13000000, 816000000, 816, 13, 1, 12 }, + { 19200000, 816000000, 680, 16, 1, 8 }, + { 26000000, 816000000, 816, 26, 1, 12 }, /* 760 MHz */ - { 12000000, 760000000, 760, 12, 0, 12 }, - { 13000000, 760000000, 760, 13, 0, 12 }, - { 19200000, 760000000, 950, 24, 0, 8 }, - { 26000000, 760000000, 760, 26, 0, 12 }, + { 12000000, 760000000, 760, 12, 1, 12 }, + { 13000000, 760000000, 760, 13, 1, 12 }, + { 19200000, 760000000, 950, 24, 1, 8 }, + { 26000000, 760000000, 760, 26, 1, 12 }, /* 750 MHz */ - { 12000000, 750000000, 750, 12, 0, 12 }, - { 13000000, 750000000, 750, 13, 0, 12 }, - { 19200000, 750000000, 625, 16, 0, 8 }, - { 26000000, 750000000, 750, 26, 0, 12 }, + { 12000000, 750000000, 750, 12, 1, 12 }, + { 13000000, 750000000, 750, 13, 1, 12 }, + { 19200000, 750000000, 625, 16, 1, 8 }, + { 26000000, 750000000, 750, 26, 1, 12 }, /* 608 MHz */ - { 12000000, 608000000, 608, 12, 0, 12 }, - { 13000000, 608000000, 608, 13, 0, 12 }, - { 19200000, 608000000, 380, 12, 0, 8 }, - { 26000000, 608000000, 608, 26, 0, 12 }, + { 12000000, 608000000, 608, 12, 1, 12 }, + { 13000000, 608000000, 608, 13, 1, 12 }, + { 19200000, 608000000, 380, 12, 1, 8 }, + { 26000000, 608000000, 608, 26, 1, 12 }, /* 456 MHz */ - { 12000000, 456000000, 456, 12, 0, 12 }, - { 13000000, 456000000, 456, 13, 0, 12 }, - { 19200000, 456000000, 380, 16, 0, 8 }, - { 26000000, 456000000, 456, 26, 0, 12 }, + { 12000000, 456000000, 456, 12, 1, 12 }, + { 13000000, 456000000, 456, 13, 1, 12 }, + { 19200000, 456000000, 380, 16, 1, 8 }, + { 26000000, 456000000, 456, 26, 1, 12 }, /* 312 MHz */ - { 12000000, 312000000, 312, 12, 0, 12 }, - { 13000000, 312000000, 312, 13, 0, 12 }, - { 19200000, 312000000, 260, 16, 0, 8 }, - { 26000000, 312000000, 312, 26, 0, 12 }, + { 12000000, 312000000, 312, 12, 1, 12 }, + { 13000000, 312000000, 312, 13, 1, 12 }, + { 19200000, 312000000, 260, 16, 1, 8 }, + { 26000000, 312000000, 312, 26, 1, 12 }, { 0, 0, 0, 0, 0, 0 }, }; +static const struct pdiv_map plle_p[] = { + { .pdiv = 1, .hw_val = 1 }, + { .pdiv = 0, .hw_val = 0 }, +}; + static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { - { 12000000, 100000000, 200, 24, 0, 0 }, + { 12000000, 100000000, 200, 24, 1, 0 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -411,6 +416,7 @@ static struct tegra_clk_pll_params pll_e_params = { .lock_mask = PLLE_MISC_LOCK, .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, .lock_delay = 0, + .pdiv_tohw = plle_p, .freq_table = pll_e_freq_table, .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_HAS_LOCK_ENABLE, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index a78f033c57e6..8493dd90f685 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -248,87 +248,87 @@ static const struct utmi_clk_param utmi_parameters[] = { }; static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { - { 12000000, 1040000000, 520, 6, 0, 8 }, - { 13000000, 1040000000, 480, 6, 0, 8 }, - { 16800000, 1040000000, 495, 8, 0, 8 }, /* actual: 1039.5 MHz */ - { 19200000, 1040000000, 325, 6, 0, 6 }, - { 26000000, 1040000000, 520, 13, 0, 8 }, - { 12000000, 832000000, 416, 6, 0, 8 }, - { 13000000, 832000000, 832, 13, 0, 8 }, - { 16800000, 832000000, 396, 8, 0, 8 }, /* actual: 831.6 MHz */ - { 19200000, 832000000, 260, 6, 0, 8 }, - { 26000000, 832000000, 416, 13, 0, 8 }, - { 12000000, 624000000, 624, 12, 0, 8 }, - { 13000000, 624000000, 624, 13, 0, 8 }, - { 16800000, 600000000, 520, 14, 0, 8 }, - { 19200000, 624000000, 520, 16, 0, 8 }, - { 26000000, 624000000, 624, 26, 0, 8 }, - { 12000000, 600000000, 600, 12, 0, 8 }, - { 13000000, 600000000, 600, 13, 0, 8 }, - { 16800000, 600000000, 500, 14, 0, 8 }, - { 19200000, 600000000, 375, 12, 0, 6 }, - { 26000000, 600000000, 600, 26, 0, 8 }, - { 12000000, 520000000, 520, 12, 0, 8 }, - { 13000000, 520000000, 520, 13, 0, 8 }, - { 16800000, 520000000, 495, 16, 0, 8 }, /* actual: 519.75 MHz */ - { 19200000, 520000000, 325, 12, 0, 6 }, - { 26000000, 520000000, 520, 26, 0, 8 }, - { 12000000, 416000000, 416, 12, 0, 8 }, - { 13000000, 416000000, 416, 13, 0, 8 }, - { 16800000, 416000000, 396, 16, 0, 8 }, /* actual: 415.8 MHz */ - { 19200000, 416000000, 260, 12, 0, 6 }, - { 26000000, 416000000, 416, 26, 0, 8 }, + { 12000000, 1040000000, 520, 6, 1, 8 }, + { 13000000, 1040000000, 480, 6, 1, 8 }, + { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */ + { 19200000, 1040000000, 325, 6, 1, 6 }, + { 26000000, 1040000000, 520, 13, 1, 8 }, + { 12000000, 832000000, 416, 6, 1, 8 }, + { 13000000, 832000000, 832, 13, 1, 8 }, + { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */ + { 19200000, 832000000, 260, 6, 1, 8 }, + { 26000000, 832000000, 416, 13, 1, 8 }, + { 12000000, 624000000, 624, 12, 1, 8 }, + { 13000000, 624000000, 624, 13, 1, 8 }, + { 16800000, 600000000, 520, 14, 1, 8 }, + { 19200000, 624000000, 520, 16, 1, 8 }, + { 26000000, 624000000, 624, 26, 1, 8 }, + { 12000000, 600000000, 600, 12, 1, 8 }, + { 13000000, 600000000, 600, 13, 1, 8 }, + { 16800000, 600000000, 500, 14, 1, 8 }, + { 19200000, 600000000, 375, 12, 1, 6 }, + { 26000000, 600000000, 600, 26, 1, 8 }, + { 12000000, 520000000, 520, 12, 1, 8 }, + { 13000000, 520000000, 520, 13, 1, 8 }, + { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */ + { 19200000, 520000000, 325, 12, 1, 6 }, + { 26000000, 520000000, 520, 26, 1, 8 }, + { 12000000, 416000000, 416, 12, 1, 8 }, + { 13000000, 416000000, 416, 13, 1, 8 }, + { 16800000, 416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */ + { 19200000, 416000000, 260, 12, 1, 6 }, + { 26000000, 416000000, 416, 26, 1, 8 }, { 0, 0, 0, 0, 0, 0 }, }; static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { - { 12000000, 666000000, 666, 12, 0, 8 }, - { 13000000, 666000000, 666, 13, 0, 8 }, - { 16800000, 666000000, 555, 14, 0, 8 }, - { 19200000, 666000000, 555, 16, 0, 8 }, - { 26000000, 666000000, 666, 26, 0, 8 }, - { 12000000, 600000000, 600, 12, 0, 8 }, - { 13000000, 600000000, 600, 13, 0, 8 }, - { 16800000, 600000000, 500, 14, 0, 8 }, - { 19200000, 600000000, 375, 12, 0, 6 }, - { 26000000, 600000000, 600, 26, 0, 8 }, + { 12000000, 666000000, 666, 12, 1, 8 }, + { 13000000, 666000000, 666, 13, 1, 8 }, + { 16800000, 666000000, 555, 14, 1, 8 }, + { 19200000, 666000000, 555, 16, 1, 8 }, + { 26000000, 666000000, 666, 26, 1, 8 }, + { 12000000, 600000000, 600, 12, 1, 8 }, + { 13000000, 600000000, 600, 13, 1, 8 }, + { 16800000, 600000000, 500, 14, 1, 8 }, + { 19200000, 600000000, 375, 12, 1, 6 }, + { 26000000, 600000000, 600, 26, 1, 8 }, { 0, 0, 0, 0, 0, 0 }, }; static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { - { 12000000, 216000000, 432, 12, 1, 8 }, - { 13000000, 216000000, 432, 13, 1, 8 }, - { 16800000, 216000000, 360, 14, 1, 8 }, - { 19200000, 216000000, 360, 16, 1, 8 }, - { 26000000, 216000000, 432, 26, 1, 8 }, + { 12000000, 216000000, 432, 12, 2, 8 }, + { 13000000, 216000000, 432, 13, 2, 8 }, + { 16800000, 216000000, 360, 14, 2, 8 }, + { 19200000, 216000000, 360, 16, 2, 8 }, + { 26000000, 216000000, 432, 26, 2, 8 }, { 0, 0, 0, 0, 0, 0 }, }; static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { - { 9600000, 564480000, 294, 5, 0, 4 }, - { 9600000, 552960000, 288, 5, 0, 4 }, - { 9600000, 24000000, 5, 2, 0, 1 }, - { 28800000, 56448000, 49, 25, 0, 1 }, - { 28800000, 73728000, 64, 25, 0, 1 }, - { 28800000, 24000000, 5, 6, 0, 1 }, + { 9600000, 564480000, 294, 5, 1, 4 }, + { 9600000, 552960000, 288, 5, 1, 4 }, + { 9600000, 24000000, 5, 2, 1, 1 }, + { 28800000, 56448000, 49, 25, 1, 1 }, + { 28800000, 73728000, 64, 25, 1, 1 }, + { 28800000, 24000000, 5, 6, 1, 1 }, { 0, 0, 0, 0, 0, 0 }, }; static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { - { 12000000, 216000000, 216, 12, 0, 4 }, - { 13000000, 216000000, 216, 13, 0, 4 }, - { 16800000, 216000000, 180, 14, 0, 4 }, - { 19200000, 216000000, 180, 16, 0, 4 }, - { 26000000, 216000000, 216, 26, 0, 4 }, - { 12000000, 594000000, 594, 12, 0, 8 }, - { 13000000, 594000000, 594, 13, 0, 8 }, - { 16800000, 594000000, 495, 14, 0, 8 }, - { 19200000, 594000000, 495, 16, 0, 8 }, - { 26000000, 594000000, 594, 26, 0, 8 }, - { 12000000, 1000000000, 1000, 12, 0, 12 }, - { 13000000, 1000000000, 1000, 13, 0, 12 }, - { 19200000, 1000000000, 625, 12, 0, 8 }, - { 26000000, 1000000000, 1000, 26, 0, 12 }, + { 12000000, 216000000, 216, 12, 1, 4 }, + { 13000000, 216000000, 216, 13, 1, 4 }, + { 16800000, 216000000, 180, 14, 1, 4 }, + { 19200000, 216000000, 180, 16, 1, 4 }, + { 26000000, 216000000, 216, 26, 1, 4 }, + { 12000000, 594000000, 594, 12, 1, 8 }, + { 13000000, 594000000, 594, 13, 1, 8 }, + { 16800000, 594000000, 495, 14, 1, 8 }, + { 19200000, 594000000, 495, 16, 1, 8 }, + { 26000000, 594000000, 594, 26, 1, 8 }, + { 12000000, 1000000000, 1000, 12, 1, 12 }, + { 13000000, 1000000000, 1000, 13, 1, 12 }, + { 19200000, 1000000000, 625, 12, 1, 8 }, + { 26000000, 1000000000, 1000, 26, 1, 12 }, { 0, 0, 0, 0, 0, 0 }, }; @@ -339,66 +339,72 @@ static const struct pdiv_map pllu_p[] = { }; static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { - { 12000000, 480000000, 960, 12, 0, 12 }, - { 13000000, 480000000, 960, 13, 0, 12 }, - { 16800000, 480000000, 400, 7, 0, 5 }, - { 19200000, 480000000, 200, 4, 0, 3 }, - { 26000000, 480000000, 960, 26, 0, 12 }, + { 12000000, 480000000, 960, 12, 1, 12 }, + { 13000000, 480000000, 960, 13, 1, 12 }, + { 16800000, 480000000, 400, 7, 1, 5 }, + { 19200000, 480000000, 200, 4, 1, 3 }, + { 26000000, 480000000, 960, 26, 1, 12 }, { 0, 0, 0, 0, 0, 0 }, }; static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { /* 1.7 GHz */ - { 12000000, 1700000000, 850, 6, 0, 8 }, - { 13000000, 1700000000, 915, 7, 0, 8 }, /* actual: 1699.2 MHz */ - { 16800000, 1700000000, 708, 7, 0, 8 }, /* actual: 1699.2 MHz */ - { 19200000, 1700000000, 885, 10, 0, 8 }, /* actual: 1699.2 MHz */ - { 26000000, 1700000000, 850, 13, 0, 8 }, + { 12000000, 1700000000, 850, 6, 1, 8 }, + { 13000000, 1700000000, 915, 7, 1, 8 }, /* actual: 1699.2 MHz */ + { 16800000, 1700000000, 708, 7, 1, 8 }, /* actual: 1699.2 MHz */ + { 19200000, 1700000000, 885, 10, 1, 8 }, /* actual: 1699.2 MHz */ + { 26000000, 1700000000, 850, 13, 1, 8 }, /* 1.6 GHz */ - { 12000000, 1600000000, 800, 6, 0, 8 }, - { 13000000, 1600000000, 738, 6, 0, 8 }, /* actual: 1599.0 MHz */ - { 16800000, 1600000000, 857, 9, 0, 8 }, /* actual: 1599.7 MHz */ - { 19200000, 1600000000, 500, 6, 0, 8 }, - { 26000000, 1600000000, 800, 13, 0, 8 }, + { 12000000, 1600000000, 800, 6, 1, 8 }, + { 13000000, 1600000000, 738, 6, 1, 8 }, /* actual: 1599.0 MHz */ + { 16800000, 1600000000, 857, 9, 1, 8 }, /* actual: 1599.7 MHz */ + { 19200000, 1600000000, 500, 6, 1, 8 }, + { 26000000, 1600000000, 800, 13, 1, 8 }, /* 1.5 GHz */ - { 12000000, 1500000000, 750, 6, 0, 8 }, - { 13000000, 1500000000, 923, 8, 0, 8 }, /* actual: 1499.8 MHz */ - { 16800000, 1500000000, 625, 7, 0, 8 }, - { 19200000, 1500000000, 625, 8, 0, 8 }, - { 26000000, 1500000000, 750, 13, 0, 8 }, + { 12000000, 1500000000, 750, 6, 1, 8 }, + { 13000000, 1500000000, 923, 8, 1, 8 }, /* actual: 1499.8 MHz */ + { 16800000, 1500000000, 625, 7, 1, 8 }, + { 19200000, 1500000000, 625, 8, 1, 8 }, + { 26000000, 1500000000, 750, 13, 1, 8 }, /* 1.4 GHz */ - { 12000000, 1400000000, 700, 6, 0, 8 }, - { 13000000, 1400000000, 969, 9, 0, 8 }, /* actual: 1399.7 MHz */ - { 16800000, 1400000000, 1000, 12, 0, 8 }, - { 19200000, 1400000000, 875, 12, 0, 8 }, - { 26000000, 1400000000, 700, 13, 0, 8 }, + { 12000000, 1400000000, 700, 6, 1, 8 }, + { 13000000, 1400000000, 969, 9, 1, 8 }, /* actual: 1399.7 MHz */ + { 16800000, 1400000000, 1000, 12, 1, 8 }, + { 19200000, 1400000000, 875, 12, 1, 8 }, + { 26000000, 1400000000, 700, 13, 1, 8 }, /* 1.3 GHz */ - { 12000000, 1300000000, 975, 9, 0, 8 }, - { 13000000, 1300000000, 1000, 10, 0, 8 }, - { 16800000, 1300000000, 928, 12, 0, 8 }, /* actual: 1299.2 MHz */ - { 19200000, 1300000000, 812, 12, 0, 8 }, /* actual: 1299.2 MHz */ - { 26000000, 1300000000, 650, 13, 0, 8 }, + { 12000000, 1300000000, 975, 9, 1, 8 }, + { 13000000, 1300000000, 1000, 10, 1, 8 }, + { 16800000, 1300000000, 928, 12, 1, 8 }, /* actual: 1299.2 MHz */ + { 19200000, 1300000000, 812, 12, 1, 8 }, /* actual: 1299.2 MHz */ + { 26000000, 1300000000, 650, 13, 1, 8 }, /* 1.2 GHz */ - { 12000000, 1200000000, 1000, 10, 0, 8 }, - { 13000000, 1200000000, 923, 10, 0, 8 }, /* actual: 1199.9 MHz */ - { 16800000, 1200000000, 1000, 14, 0, 8 }, - { 19200000, 1200000000, 1000, 16, 0, 8 }, - { 26000000, 1200000000, 600, 13, 0, 8 }, + { 12000000, 1200000000, 1000, 10, 1, 8 }, + { 13000000, 1200000000, 923, 10, 1, 8 }, /* actual: 1199.9 MHz */ + { 16800000, 1200000000, 1000, 14, 1, 8 }, + { 19200000, 1200000000, 1000, 16, 1, 8 }, + { 26000000, 1200000000, 600, 13, 1, 8 }, /* 1.1 GHz */ - { 12000000, 1100000000, 825, 9, 0, 8 }, - { 13000000, 1100000000, 846, 10, 0, 8 }, /* actual: 1099.8 MHz */ - { 16800000, 1100000000, 982, 15, 0, 8 }, /* actual: 1099.8 MHz */ - { 19200000, 1100000000, 859, 15, 0, 8 }, /* actual: 1099.5 MHz */ - { 26000000, 1100000000, 550, 13, 0, 8 }, + { 12000000, 1100000000, 825, 9, 1, 8 }, + { 13000000, 1100000000, 846, 10, 1, 8 }, /* actual: 1099.8 MHz */ + { 16800000, 1100000000, 982, 15, 1, 8 }, /* actual: 1099.8 MHz */ + { 19200000, 1100000000, 859, 15, 1, 8 }, /* actual: 1099.5 MHz */ + { 26000000, 1100000000, 550, 13, 1, 8 }, /* 1 GHz */ - { 12000000, 1000000000, 1000, 12, 0, 8 }, - { 13000000, 1000000000, 1000, 13, 0, 8 }, - { 16800000, 1000000000, 833, 14, 0, 8 }, /* actual: 999.6 MHz */ - { 19200000, 1000000000, 625, 12, 0, 8 }, - { 26000000, 1000000000, 1000, 26, 0, 8 }, + { 12000000, 1000000000, 1000, 12, 1, 8 }, + { 13000000, 1000000000, 1000, 13, 1, 8 }, + { 16800000, 1000000000, 833, 14, 1, 8 }, /* actual: 999.6 MHz */ + { 19200000, 1000000000, 625, 12, 1, 8 }, + { 26000000, 1000000000, 1000, 26, 1, 8 }, { 0, 0, 0, 0, 0, 0 }, }; +static const struct pdiv_map plle_p[] = { + { .pdiv = 18, .hw_val = 18 }, + { .pdiv = 24, .hw_val = 24 }, + { .pdiv = 0, .hw_val = 0 }, +}; + static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { /* PLLE special case: use cpcon field to store cml divider value */ { 12000000, 100000000, 150, 1, 18, 11 }, @@ -573,6 +579,7 @@ static struct tegra_clk_pll_params pll_e_params = { .lock_mask = PLLE_MISC_LOCK, .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, .lock_delay = 300, + .pdiv_tohw = plle_p, .freq_table = pll_e_freq_table, .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC, |