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path: root/drivers/clk/tegra/clk-tegra20.c
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Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
-rw-r--r--drivers/clk/tegra/clk-tegra20.c150
1 files changed, 78 insertions, 72 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index b49d94bc0b8f..7a48e986c4c9 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -166,114 +166,119 @@ static DEFINE_SPINLOCK(emc_lock);
static struct clk **clks;
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
- { 12000000, 600000000, 600, 12, 0, 8 },
- { 13000000, 600000000, 600, 13, 0, 8 },
- { 19200000, 600000000, 500, 16, 0, 6 },
- { 26000000, 600000000, 600, 26, 0, 8 },
+ { 12000000, 600000000, 600, 12, 1, 8 },
+ { 13000000, 600000000, 600, 13, 1, 8 },
+ { 19200000, 600000000, 500, 16, 1, 6 },
+ { 26000000, 600000000, 600, 26, 1, 8 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
- { 12000000, 666000000, 666, 12, 0, 8 },
- { 13000000, 666000000, 666, 13, 0, 8 },
- { 19200000, 666000000, 555, 16, 0, 8 },
- { 26000000, 666000000, 666, 26, 0, 8 },
- { 12000000, 600000000, 600, 12, 0, 8 },
- { 13000000, 600000000, 600, 13, 0, 8 },
- { 19200000, 600000000, 375, 12, 0, 6 },
- { 26000000, 600000000, 600, 26, 0, 8 },
+ { 12000000, 666000000, 666, 12, 1, 8 },
+ { 13000000, 666000000, 666, 13, 1, 8 },
+ { 19200000, 666000000, 555, 16, 1, 8 },
+ { 26000000, 666000000, 666, 26, 1, 8 },
+ { 12000000, 600000000, 600, 12, 1, 8 },
+ { 13000000, 600000000, 600, 13, 1, 8 },
+ { 19200000, 600000000, 375, 12, 1, 6 },
+ { 26000000, 600000000, 600, 26, 1, 8 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
- { 12000000, 216000000, 432, 12, 1, 8 },
- { 13000000, 216000000, 432, 13, 1, 8 },
- { 19200000, 216000000, 90, 4, 1, 1 },
- { 26000000, 216000000, 432, 26, 1, 8 },
- { 12000000, 432000000, 432, 12, 0, 8 },
- { 13000000, 432000000, 432, 13, 0, 8 },
- { 19200000, 432000000, 90, 4, 0, 1 },
- { 26000000, 432000000, 432, 26, 0, 8 },
+ { 12000000, 216000000, 432, 12, 2, 8 },
+ { 13000000, 216000000, 432, 13, 2, 8 },
+ { 19200000, 216000000, 90, 4, 2, 1 },
+ { 26000000, 216000000, 432, 26, 2, 8 },
+ { 12000000, 432000000, 432, 12, 1, 8 },
+ { 13000000, 432000000, 432, 13, 1, 8 },
+ { 19200000, 432000000, 90, 4, 1, 1 },
+ { 26000000, 432000000, 432, 26, 1, 8 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
- { 28800000, 56448000, 49, 25, 0, 1 },
- { 28800000, 73728000, 64, 25, 0, 1 },
- { 28800000, 24000000, 5, 6, 0, 1 },
+ { 28800000, 56448000, 49, 25, 1, 1 },
+ { 28800000, 73728000, 64, 25, 1, 1 },
+ { 28800000, 24000000, 5, 6, 1, 1 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
- { 12000000, 216000000, 216, 12, 0, 4 },
- { 13000000, 216000000, 216, 13, 0, 4 },
- { 19200000, 216000000, 135, 12, 0, 3 },
- { 26000000, 216000000, 216, 26, 0, 4 },
- { 12000000, 594000000, 594, 12, 0, 8 },
- { 13000000, 594000000, 594, 13, 0, 8 },
- { 19200000, 594000000, 495, 16, 0, 8 },
- { 26000000, 594000000, 594, 26, 0, 8 },
- { 12000000, 1000000000, 1000, 12, 0, 12 },
- { 13000000, 1000000000, 1000, 13, 0, 12 },
- { 19200000, 1000000000, 625, 12, 0, 8 },
- { 26000000, 1000000000, 1000, 26, 0, 12 },
+ { 12000000, 216000000, 216, 12, 1, 4 },
+ { 13000000, 216000000, 216, 13, 1, 4 },
+ { 19200000, 216000000, 135, 12, 1, 3 },
+ { 26000000, 216000000, 216, 26, 1, 4 },
+ { 12000000, 594000000, 594, 12, 1, 8 },
+ { 13000000, 594000000, 594, 13, 1, 8 },
+ { 19200000, 594000000, 495, 16, 1, 8 },
+ { 26000000, 594000000, 594, 26, 1, 8 },
+ { 12000000, 1000000000, 1000, 12, 1, 12 },
+ { 13000000, 1000000000, 1000, 13, 1, 12 },
+ { 19200000, 1000000000, 625, 12, 1, 8 },
+ { 26000000, 1000000000, 1000, 26, 1, 12 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
- { 12000000, 480000000, 960, 12, 0, 0 },
- { 13000000, 480000000, 960, 13, 0, 0 },
- { 19200000, 480000000, 200, 4, 0, 0 },
- { 26000000, 480000000, 960, 26, 0, 0 },
+ { 12000000, 480000000, 960, 12, 1, 0 },
+ { 13000000, 480000000, 960, 13, 1, 0 },
+ { 19200000, 480000000, 200, 4, 1, 0 },
+ { 26000000, 480000000, 960, 26, 1, 0 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
/* 1 GHz */
- { 12000000, 1000000000, 1000, 12, 0, 12 },
- { 13000000, 1000000000, 1000, 13, 0, 12 },
- { 19200000, 1000000000, 625, 12, 0, 8 },
- { 26000000, 1000000000, 1000, 26, 0, 12 },
+ { 12000000, 1000000000, 1000, 12, 1, 12 },
+ { 13000000, 1000000000, 1000, 13, 1, 12 },
+ { 19200000, 1000000000, 625, 12, 1, 8 },
+ { 26000000, 1000000000, 1000, 26, 1, 12 },
/* 912 MHz */
- { 12000000, 912000000, 912, 12, 0, 12 },
- { 13000000, 912000000, 912, 13, 0, 12 },
- { 19200000, 912000000, 760, 16, 0, 8 },
- { 26000000, 912000000, 912, 26, 0, 12 },
+ { 12000000, 912000000, 912, 12, 1, 12 },
+ { 13000000, 912000000, 912, 13, 1, 12 },
+ { 19200000, 912000000, 760, 16, 1, 8 },
+ { 26000000, 912000000, 912, 26, 1, 12 },
/* 816 MHz */
- { 12000000, 816000000, 816, 12, 0, 12 },
- { 13000000, 816000000, 816, 13, 0, 12 },
- { 19200000, 816000000, 680, 16, 0, 8 },
- { 26000000, 816000000, 816, 26, 0, 12 },
+ { 12000000, 816000000, 816, 12, 1, 12 },
+ { 13000000, 816000000, 816, 13, 1, 12 },
+ { 19200000, 816000000, 680, 16, 1, 8 },
+ { 26000000, 816000000, 816, 26, 1, 12 },
/* 760 MHz */
- { 12000000, 760000000, 760, 12, 0, 12 },
- { 13000000, 760000000, 760, 13, 0, 12 },
- { 19200000, 760000000, 950, 24, 0, 8 },
- { 26000000, 760000000, 760, 26, 0, 12 },
+ { 12000000, 760000000, 760, 12, 1, 12 },
+ { 13000000, 760000000, 760, 13, 1, 12 },
+ { 19200000, 760000000, 950, 24, 1, 8 },
+ { 26000000, 760000000, 760, 26, 1, 12 },
/* 750 MHz */
- { 12000000, 750000000, 750, 12, 0, 12 },
- { 13000000, 750000000, 750, 13, 0, 12 },
- { 19200000, 750000000, 625, 16, 0, 8 },
- { 26000000, 750000000, 750, 26, 0, 12 },
+ { 12000000, 750000000, 750, 12, 1, 12 },
+ { 13000000, 750000000, 750, 13, 1, 12 },
+ { 19200000, 750000000, 625, 16, 1, 8 },
+ { 26000000, 750000000, 750, 26, 1, 12 },
/* 608 MHz */
- { 12000000, 608000000, 608, 12, 0, 12 },
- { 13000000, 608000000, 608, 13, 0, 12 },
- { 19200000, 608000000, 380, 12, 0, 8 },
- { 26000000, 608000000, 608, 26, 0, 12 },
+ { 12000000, 608000000, 608, 12, 1, 12 },
+ { 13000000, 608000000, 608, 13, 1, 12 },
+ { 19200000, 608000000, 380, 12, 1, 8 },
+ { 26000000, 608000000, 608, 26, 1, 12 },
/* 456 MHz */
- { 12000000, 456000000, 456, 12, 0, 12 },
- { 13000000, 456000000, 456, 13, 0, 12 },
- { 19200000, 456000000, 380, 16, 0, 8 },
- { 26000000, 456000000, 456, 26, 0, 12 },
+ { 12000000, 456000000, 456, 12, 1, 12 },
+ { 13000000, 456000000, 456, 13, 1, 12 },
+ { 19200000, 456000000, 380, 16, 1, 8 },
+ { 26000000, 456000000, 456, 26, 1, 12 },
/* 312 MHz */
- { 12000000, 312000000, 312, 12, 0, 12 },
- { 13000000, 312000000, 312, 13, 0, 12 },
- { 19200000, 312000000, 260, 16, 0, 8 },
- { 26000000, 312000000, 312, 26, 0, 12 },
+ { 12000000, 312000000, 312, 12, 1, 12 },
+ { 13000000, 312000000, 312, 13, 1, 12 },
+ { 19200000, 312000000, 260, 16, 1, 8 },
+ { 26000000, 312000000, 312, 26, 1, 12 },
{ 0, 0, 0, 0, 0, 0 },
};
+static const struct pdiv_map plle_p[] = {
+ { .pdiv = 1, .hw_val = 1 },
+ { .pdiv = 0, .hw_val = 0 },
+};
+
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
- { 12000000, 100000000, 200, 24, 0, 0 },
+ { 12000000, 100000000, 200, 24, 1, 0 },
{ 0, 0, 0, 0, 0, 0 },
};
@@ -411,6 +416,7 @@ static struct tegra_clk_pll_params pll_e_params = {
.lock_mask = PLLE_MISC_LOCK,
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
.lock_delay = 0,
+ .pdiv_tohw = plle_p,
.freq_table = pll_e_freq_table,
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC |
TEGRA_PLL_HAS_LOCK_ENABLE,
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.