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2023-06-21ARM: dts: Move .dts files to vendor sub-directoriesRob Herring1-845/+0
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
2023-02-09ARM: dts: uniphier: Add syscon-uhs-mode to SD nodeKunihiko Hayashi1-1/+2
Add sociopnext,syscon-uhs-mode prpperty to the SD node to refer the handle of the control logic node. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-5-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-09ARM: dts: uniphier: Add syscon compatible string to soc-glue-debugKunihiko Hayashi1-1/+1
Add "syscon" compatible string to the nodes for soc-glue-debug according to the DT schema. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-4-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-09ARM: dts: uniphier: Add missing reg properties for glue layerKunihiko Hayashi1-0/+4
The nodes for glue layers should include "reg" property. Add the property according to the DT schema. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-3-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-09ARM: dts: uniphier: Align node names for SoC-dependent controller and PHYs with bindingsKunihiko Hayashi1-21/+21
The node names for SoC-dependent controllers and PHYs should be generic ones according to the DT schemas. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-2-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Add ahci controller nodes for PXs2Kunihiko Hayashi1-0/+40
Add ahci core controller and glue layer nodes including reset-controller and sata-phy. This supports for PXs2 and the boards without PXs2 vodka board that doesn't implement any SATA connectors. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-8-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Use GIC interrupt definitionsKunihiko Hayashi1-25/+31
Use human-readable definitions for GIC interrupt type and flag, instead of hard-coding the numbers. No functional change. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-6-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Rename usb-glue node for USB3 to usb-controllerKunihiko Hayashi1-2/+2
This "usb-glue" stands for an external controller associated with USB core, however, this is not common. So rename to "usb-controller". Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-4-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Rename pvtctl node to thermal-sensorKunihiko Hayashi1-1/+1
The pvtctl node belongs to thermal-sensor, so the node name should be renamed to thermal-sensor. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-2-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-08-02ARM: dts: uniphier: Fix USB interrupts for PXs2 SoCKunihiko Hayashi1-4/+4
An interrupt for USB device are shared with USB host. Set interrupt-names property to common "dwc_usb3" instead of "host" and "peripheral". Cc: stable@vger.kernel.org Fixes: 45be1573ad19 ("ARM: dts: uniphier: Add USB3 controller nodes") Reported-by: Ryuta NAKANISHI <nakanishi.ryuta@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-22ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for RTL8211EKunihiko Hayashi1-1/+1
UniPhier PXs2 boards have RTL8211E ethernet phy, and the phy have the RX/TX delays of RGMII interface using pull-ups on the RXDLY and TXDLY pins. After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay config"), the delays are working correctly, however, "rgmii" means no delay and the phy doesn't work. So need to set the phy-mode to "rgmii-id" to show that RX/TX delays are enabled. Fixes: e3cc931921d2 ("ARM: dts: uniphier: add AVE ethernet node") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-05-04ARM: dts: uniphier: add #address-cells and #size-cells to SPI nodesMasahiro Yamada1-0/+4
Documentation/devicetree/bindings/spi/spi-uniphier.txt requires #address-cells and #size-cells, but they are missing in actual DT files. Also, 'make ARCH=arm dtbs_check' is really noisy. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-04ARM: dts: uniphier: Add XDMAC nodeKunihiko Hayashi1-0/+8
Add external DMA controller support implemented in UniPhier SoCs. This supports for Pro4, Pro5 and PXs2. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-03-17ARM: dts: uniphier: Set SCSSI clock and reset IDs for each channelKunihiko Hayashi1-2/+2
Currently common clock and reset IDs were used, however, each clock and reset ID should be used for each channel. Pro5 and PXs2 are affected by this fix, but the SCSSI clock gate of Pro5 is common to all channels. Fixes: 92fa4f4cc2cd ("ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29ARM: dts: uniphier: rename cache controller nodes to follow json-schemaMasahiro Yamada1-1/+1
Follow the standard nodename pattern "^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in schemas/cache-controller.yaml of dt-schema. Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm dtbs_check' will show warnings like this: l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29ARM: dts: uniphier: rename NAND node names to follow json-schemaMasahiro Yamada1-1/+1
Follow the standard nodename pattern "^nand-controller(@.*)?" defined in Documentation/devicetree/bindings/mtd/nand-controller.yaml Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm dtbs_check' will show warnings like this: nand@68000000: $nodename:0: 'nand@68000000' does not match '^nand-controller(@.*)?' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29ARM: dts: uniphier: rename aidet node names to follow json-schemaMasahiro Yamada1-1/+1
Follow the standard nodename pattern "^interrupt-controller(@[0-9a-f,]+)*$" defined in schemas/interrupt-controller.yaml of dt-schema. Otherwise, after the dt-binding is converted to json-schema, make ARCH=arm dtbs_check' will show warnings like this: aidet@5fc20000: $nodename:0: 'aidet@5fc20000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29ARM: dts: uniphier: change SD/eMMC node names to follow json-schemaMasahiro Yamada1-2/+2
Follow the standard nodename pattern "^mmc(@.*)?$" defined in Documentation/devicetree/bindings/mmc/mmc-controller.yaml Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm dtbs_check' will show warnings like this: sdhc@5a000000: $nodename:0: 'sdhc@5a000000' does not match '^mmc(@.*)?$' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-18ARM: dts: uniphier: add reset-names to NAND controller nodeMasahiro Yamada1-1/+2
The Denali NAND controller IP has separate reset control for the controller core and registers. Add the reset-names, and one more phandle accordingly. This is the approved DT-binding. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-26ARM: dts: uniphier: update to new Denali NAND bindingMasahiro Yamada1-1/+3
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips"), the Denali NAND controller driver migrated to the new controller/chip representation. Update DT for it. In the new binding, the number of connected chips are described in DT instead of run-time probed. I added just one chip to the reference boards, where we do not know if the on-board NAND device is a single chip or multiple chips. If we added too many chips into DT, it would end up with the timeout error in nand_scan_ident(). I changed all the pinctrl properties to use the single CS. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-27ARM: dts: uniphier: Add all CPUs in cooling mapsViresh Kumar1-2/+4
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-04ARM: dts: uniphier: Add USB3 controller nodesKunihiko Hayashi1-0/+180
Add USB3 controller nodes including usb-core, resets, regulator, ss-phy and hs-phy. This supports for Pro4, PXs2 and the boards. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-03ARM: dts: uniphier: add SD/eMMC controller nodesMasahiro Yamada1-0/+34
Add SD controller nodes for LD4, Pro4, sLD8, Pro5, and PXs2. This is also used as an eMMC controller for LD4, Pro4, and sLD8. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-28ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCsKunihiko Hayashi1-0/+22
Add nodes of SPI controller for LD4, Pro4, sLD8, Pro5 and PXs2. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-28ARM: uniphier: dts: add more clocks to Denali NAND controller nodeMasahiro Yamada1-1/+2
Catch up with the new binding of the Denali IP where three clocks, "nand", "nand_x", "ecc" are required. For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they are both 200MHz. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-19ARM: dts: uniphier: Add missing cooling device properties for CPUsViresh Kumar1-0/+3
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-25ARM: dts: uniphier: add syscon-phy-mode property to each ethernet nodeKunihiko Hayashi1-0/+1
Add syscon-phy-mode property specifying a phandle of system controller to each ethernet node. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-25ARM: dts: uniphier: add required clocks and resets to Pro4 ethernet nodeKunihiko Hayashi1-0/+2
The GIO clock/reset, Another MAC clock, and the PHY clock are required for the ethernet of Pro4 SoC. And add clock-names and reset-names to the ethernet node of PXs2 since we need to distinguish clocks and resets now. Suggested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-21ARM: dts: uniphier: add syscon property for UniPhier sound systemKatsuhiro Suzuki1-1/+2
This patch adds syscon property for specifying soc-glue core into device-tree of PXs2 SoC. Currently, soc-glue core is used for changing the state of S/PDIF signal output pin to signal output state or Hi-Z state. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-15ARM: dts: uniphier: add sound node for PXs2Katsuhiro Suzuki1-0/+54
This patch adds audio controller, external codec and simple card node of UniPhier AIO sound system for PXs2 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-15ARM: dts: uniphier: use proper SPDX-License-Identifier styleMasahiro Yamada1-8/+6
According to Documentation/process/license-rules.rst, move the SPDX License Identifier to the very top of the file. I used C++ comment style not only for the SPDX line but for the entire block because this seems Linus' preference [1]. I also dropped the parentheses to follow the examples in that document. [1] https://lkml.org/lkml/2017/11/25/133 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-15ARM: dts: uniphier: add AVE ethernet nodeKunihiko Hayashi1-0/+18
Add nodes of the AVE ethernet controller for Pro4, PXs2, LD6b SoCs and the boards. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-12ARM: dts: uniphier: add efuse node for UniPhier 32bit SoCKeiji Hayashibara1-0/+18
Add efuse node for UniPhier LD4, Pro4, sLD8, Pro5 and PXs2. This efuse node is included in soc-glue. Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-12ARM: dts: uniphier: use macros in dt-bindings headerMasahiro Yamada1-0/+1
The dt-bindings header was applied to the driver subsystem. I had to wait for a merge window to use it from DT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-24ARM: dts: uniphier: add resets propertiesMasahiro Yamada1-0/+12
Add resets properties to all nodes that have reset lines. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-24ARM: dts: uniphier: add GPIO controller nodesMasahiro Yamada1-0/+17
The GPIO controller also acts as an interrupt controller and the interrupt lines are connected to the AIDET block. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15ARM: dts: uniphier: fix W=2 build warningsMasahiro Yamada1-2/+2
Fix warnings like follows: Warning (node_name_chars_strict): Character '_' not recommended in ... Commit 8654cb8d0371 ("dtc: update warning settings for new bus and node/property name checks") says these checks are a bit subjective, but Rob also says to not add new W=2 warnings. The exising warnings should be fixed in order to catch new ones easily. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15ARM: dts: uniphier: add nodes of thermal monitor and thermal zone for PXs2Kunihiko Hayashi1-4/+43
Add nodes of thermal monitor and thermal zone for UniPhier PXs2 SoC. The thermal monitor node is included in sysctrl. Since the efuse might not have a calibrated value of thermal monitor, this patch gives the default value for PXs2. Furthermore, add cpuN labels for reference in cooling-device property. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28ARM: dts: uniphier: fix size of sdctrl nodesMasahiro Yamada1-1/+1
All registers are located within 0x400 size from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28ARM: dts: uniphier: add AIDET nodesMasahiro Yamada1-0/+7
Add UniPhier AIDET (ARM Interrupt Detector) nodes to support active low interrupts. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-16ARM: dts: uniphier: add Denali NAND controller nodeMasahiro Yamada1-0/+11
Add NAND controller node to LD4, Pro4, sLD8, Pro5, and PXs2. Set up pinctrl to enable 2 chip select lines except Pro4. The CS1 for Pro4 is multiplexed with other peripherals such as UART2, so I did not enable it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-16ARM: dts: uniphier use #include instead of /include/Masahiro Yamada1-1/+1
To include dt-bindings headers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-06ARM: dts: uniphier: use SPDX-License-IdentifierMasahiro Yamada1-37/+1
Follow the recent trend for the license description, and fix the wrongly stated X11 to MIT. The X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-06ARM: dts: uniphier: fix simple-bus unit address format errorMasahiro Yamada1-1/+1
Compiling the UniPhier DT files with W=1, DTC warns like follows: Warning (simple_bus_reg): Node /soc/system-bus@58c00000/support_card@1,1f00000/ethernet@00000000 simple-bus unit address format error, expected "0" Warning (simple_bus_reg): Node /soc/system-bus@58c00000/support_card@1,1f00000/uart@000b0000 simple-bus unit address format error, expected "b0000" Warning (simple_bus_reg): Node /soc/smpctrl@59800000 simple-bus unit address format error, expected "59801000" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-06ARM: dts: uniphier: Use - instead of @ for DT OPP entriesViresh Kumar1-8/+8
Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-03-07ARM: dts: uniphier: remove skeleton.dtsi inclusionMasahiro Yamada1-2/+2
Commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated") declared that skeleton.dtsi was deprecated. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-11-05ARM: dts: uniphier: make 32bit SoC DTSI linearMasahiro Yamada1-115/+238
I notice some mistakes in the SoC DTSI; wrong interrupts properties of timer nodes, mismatch between the node name and the compatible for sdctrl block. Given those problems fixed, the common parts among SoCs are less than I had first expected. The more and more property overrides are making the SoC DTSI unreadable. Stretch out the SoC DTSI files and fix the following: - Fix the 3rd cell of the interrupts property of the timer nodes for Pro4, Pro5, PXs2 - Fix the node name mioctrl to sdctrl for Pro5, PXs2 - Fix the second region of l2 node for PXs2 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-11-05ARM: dts: uniphier: add CPU clocks and OPP table for PXs2 SoCMasahiro Yamada1-0/+46
Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2016-10-22ARM: dts: uniphier: change MIO node to SD control nodeMasahiro Yamada1-2/+2
I made a mistake bacuse the Media I/O block is not implemented in these SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-31ARM: dts: uniphier: use clock/reset controllersMasahiro Yamada1-19/+31
The UniPhier reset controller driver has been merged. Enable it. Also, replace the fixed-rate clocks with the dedicated clock drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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