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path: root/drivers/clk/imx/clk.h (follow)
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2023-08-14clk: imx: pllv4: Fix SPLL2 MULT rangeYe Li1-0/+1
The SPLL2 on iMX8ULP is different with other frac PLLs, it can support VCO from 650Mhz to 1Ghz. According to RM, the MULT is using a range from 27 to 54, not some fixed values. If using current PLL implementation, some clock rate can't be supported. Fix the issue by adding new type for the SPLL2 and use MULT range to replace MULT table Fixes: 5f0601c47c33 ("clk: imx: Update the pllv4 to support imx8ulp") Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230625123340.4067536-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-05-18clk: imx: drop imx_unregister_clocksPeng Fan1-1/+0
There is no user using imx_unregister_clocks, so drop it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230506090856.3599035-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx8ulp: Add divider closest support to get more accurate clock rateJacky Bai1-0/+9
If a divider's parent clock has fractional part, it will hard to round out a more accurate clock rate for this divider, add the 'CLK_DIVIDER_ROUND_CLOSEST' flags for such divider to get a more accurate clock rate. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: fracn-gppll: support integer pllPeng Fan1-0/+7
The fracn gppll could be configured in FRAC or INTEGER mode during hardware design. The current driver only support FRAC mode, while this patch introduces INTEGER support. When the PLL is INTEGER pll, there is no mfn, mfd, the calculation is as below: Fvco_clk = (Fref / DIV[RDIV] ) * DIV[MFI] Fclko_odiv = Fvco_clk / DIV[ODIV] In this patch, we reuse the FRAC pll logic with some condition check to simplify the driver Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-03clk: imx: drop duplicated macroPeng Fan1-3/+0
Drop duplicated macro definition Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403082728.3199849-1-peng.fan@oss.nxp.com
2023-03-31clk: imx: Add imx8m_clk_hw_composite_flags macroAdam Ford1-0/+4
In order to set custom flags to imx8m_clk_hw_composite, split it off into a separate macro which can accept additional flags. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-3-aford173@gmail.com
2023-01-31clk: imx: add imx_obtain_fixed_of_clock()Oleksij Rempel1-0/+3
Add imx_obtain_fixed_of_clock() to optionally add clock not configured in the devicetree. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-15-o.rempel@pengutronix.de
2023-01-31clk: imx: add clk-gpr-mux driverOleksij Rempel1-0/+5
Almost(?) every i.MX variant has clk mux for ethernet (rgmii/rmii) reference clock located in the GPR1 register. So far this clk is configured in different ways: - mach-imx6q is doing mux configuration based on ptp vs enet_ref clk comparison. - mach-imx7d is setting mux to PAD for all boards - mach-imx6ul is setting mux to internal clock for all boards. Since we have imx7d and imx6ul board variants which do not work with configurations forced by kernel mach code, we need to implement this clk mux properly as part of the clk framework. Which is done by this patch. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-2-o.rempel@pengutronix.de
2023-01-29clk: imx: remove clk_count of imx_register_uart_clocksPeng Fan1-2/+2
The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-4-peng.fan@oss.nxp.com
2022-11-25clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()Dario Binacchi1-2/+1
The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the function, and will allow it to be used not only for fixed rate clocks but also in wider contexts. No functional changes intended. The replacements were made with the following command: grep -rl 'imx_obtain_fixed_clk_hw' ./ | \ xargs sed -i 's/imx_obtain_fixed_clk_hw/imx_get_clk_hw_by_name/g' Tested on a BSH SystemMaster (SMM) S2 board. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20221113180839.1625832-1-dario.binacchi@amarulasolutions.com
2022-09-19clk: imx: add i.MX93 clk gatePeng Fan1-0/+4
i.MX93 LPCG is different from i.MX8M CCGR. Although imx_clk_hw_gate4_flags is used here, it not strictly match i.MX93. i.MX93 has such design: - LPCG_DIRECT use BIT0 as on/off gate when LPCG_AUTHEN CPU_LPM is 0 - LPCG_LPM_CUR use BIT[2:0] as on/off gate when LPCG_AUTHEN CPU_LPM is 1 The current implementation suppose CPU_LPM is 0, and use LPCG_DIRECT BIT[1:0] as on/off gate. Although BIT1 is touched, actually BIT1 is reserved. And imx_clk_hw_gate4_flags use mask 0x3 to determine whether the clk is enabled or not, but i.MX93 LPCG only use BIT0 to control when CPU_LPM is 0. So clk disabled unused during kernel boot not able to gate off the unused clocks. To match i.MX93 LPCG, introduce imx93_clk_gate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220830033137.4149542-6-peng.fan@oss.nxp.com
2022-09-19clk: imx: clk-composite-93: check white_listPeng Fan1-2/+3
The CCM ROOT AUTHEN register WHITE_LIST indicate: Each bit in this field represent for one domain. Bit16~Bit31 represent for DOMAIN0~DOMAIN15 respectively. Only corresponding bit of the domains is set to 1 can change the registers of this Clock Root. i.MX93 DID is 3, so if BIT(3 + WHITE_LIST_SHIFT) is 0, the clk should be set to read only. To make the imx93_clk_composite_flags be reusable, add a new parameter named did(domain id); Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220830033137.4149542-5-peng.fan@oss.nxp.com
2022-04-12clk: imx: add mcore_booted module paratemterPeng Fan1-0/+1
Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX8M, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and CCGR (clock gating) to gate clocks to peripherals. As below: anatop->ccm->ccgr->peripheral Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for CCGR and CCM, auxiliary core normally only use CCGR hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux. Per NXP hardware design, because CCGR already support gate to peripherals, and clk root gate power leakage is negligible. So when in AMP case, we could not register the clk root gate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220228124112.3974242-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: support fracn gppllPeng Fan1-0/+21
This PLL module is a Fractional-N synthesizer, supporting 30-bit numerator and denominator. Numerator is a signed number. It has feature to adjust fractional portion of feedback divider dynamically. This fracn gppll is used in i.MX93. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220228020908.2810346-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: add i.MX93 composite clkPeng Fan1-0/+9
i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here is to combine all these into one composite clk and simplify clk tree. i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220228020908.2810346-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-11-05clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular compositesAlexander Stein1-2/+2
Only imx8m_clk_hw_composite_core needs to set this flag. Fixes: a60fe746df94 ("clk: imx: Rework all imx_clk_hw_composite wrappers") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103123947.3222443-1-alexander.stein@ew.tq-group.com Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-30clk: imx: Update the pfdv2 for 8ulp specific supportJacky Bai1-2/+7
On i.MX8ULP, the 'CLK_SET_RATE_PARENT' flag should NOT be set and according to the laest RM, the PFD divider value range seems will be changed in the future, so update the pfdv2 to include the specific support for i.MX8ULP. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-8-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-09-30clk: imx: Update the compsite driver to support imx8ulpJacky Bai1-0/+6
On i.MX8ULP, some peripherals have a sw_rst control resides in the per device PCC clock control register, all others are same as i.MX7ULP, so update the 7ulp clock composite driver to support i.MX8ULP to maxmimize the code reuse. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-4-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-09-30clk: imx: Update the pllv4 to support imx8ulpJacky Bai1-2/+7
The PLLs used on i.MX8ULP is mostly the same as on i.MX7ULP, except the PLL register offset is changed. Change the PLLv4 driver for code reuse on i.MX7ULP and i.MX8ULP. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-3-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-09-30clk: imx: Rework imx_clk_hw_pll14xx wrapperAbel Vesa1-7/+3
It looks much cleaner to just have a macro compared to having a function that passes NULL as dev to the lower-level imx_dev_clk_hw_pll14xx. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-9-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2021-09-30clk: imx: Rework all imx_clk_hw_composite wrappersAbel Vesa1-30/+34
Rather than having multiple different macros for each different type of imx8m_clk_hw_composite, implement them in such a way so we can take advantage the most of the already defined simpler types. Basically, we end up having one low-level __imx8m_clk_hw_composite function, a wrapper to simplify the parents related arguments called _imx8m_clk_hw_composite and then all the types can use those for each specific case. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-8-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2021-09-30clk: imx: Rework all clk_hw_register_divider wrappersAbel Vesa1-18/+11
Instead of having multiple inline functions that were calling clk_hw_register_divider, implement a generic low-level __imx_clk_hw_divider and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-7-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2021-09-30clk: imx: Rework all clk_hw_register_mux wrappersAbel Vesa1-46/+22
Instead of having multiple inline functions that were calling clk_hw_register_mux, implement a generic low-level __imx_clk_hw_mux and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-6-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2021-09-30clk: imx: Rework all clk_hw_register_gate2 wrappersAbel Vesa1-51/+26
Instead of having multiple inline functions that were calling clk_hw_register_gate2, implement a generic low-level __imx_clk_hw_gate2 and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-5-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2021-09-17clk: imx: Rework all clk_hw_register_gate wrappersAbel Vesa1-41/+23
Instead of having multiple inline functions that were calling clk_hw_register_gate, implement a generic low-level __imx_clk_hw_gate and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-4-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2021-09-17clk: imx: Make mux/mux2 clk based helpers use clk_hw based onesAbel Vesa1-20/+6
Implement the clk based helpers as macros rather than as inline functions. Once all the provider drivers have switch to clk_hw, all the clk based macros will go away. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-3-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2021-09-17clk: imx: Remove unused helpersAbel Vesa1-103/+0
Remove all the helpers that are not referenced anywhere anymore. Most of them are not clk_hw based. The rest are passing the device as an argument and were intented for BLK_CTL driver usage, but that is not the case anymore since the BLK_CTL is (or will be) implemented outside of CCF. - imx_clk_divider2 - imx_clk_gate2_shared2 - imx_clk_gate3 - imx_clk_gate4 - imx_clk_frac_pll - imx_clk_sscg_pll - imx_clk_pll14xx - imx_clk_pll14xx - imx_clk_divider2_flags - imx_dev_clk_hw_gate - imx_dev_clk_hw_gate_shared - imx_clk_gate3_flags - imx_clk_gate4_flags - imx_dev_clk_hw_mux - imx_clk_mux2 - imx_dev_clk_hw_mux_flags - imx8m_clk_composite_flags - __imx8m_clk_composite - imx8m_clk_composite - imx8m_clk_composite_critical Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-2-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2021-08-24clk: imx8m: fix clock tree update of TF-A managed clocksAhmad Fatoum1-2/+14
On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and then does clk_set_parent on the DDR muxes to synchronize the clock tree. Since 936c383673b9 ("clk: imx: fix composite peripheral flags"), these TF-A managed muxes have SET_PARENT_GATE set, which results in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY: echo 25000000 > userspace/set_freq imx8m-ddrc-devfreq 3d400000.memory-controller: failed to set dram_apb parent: -16 Fix this by adding a new i.MX composite flag for firmware managed clocks, which clears SET_PARENT_GATE. This is safe to do, because updating the Linux clock tree to reflect reality will always be glitch-free. Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210810151432.9228-1-a.fatoum@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-04-04clk: imx: Fix reparenting of UARTs not associated with stdoutAdam Ford1-2/+2
Most if not all i.MX SoC's call a function which enables all UARTS. This is a problem for users who need to re-parent the clock source, because any attempt to change the parent results in an busy error due to the fact that the clocks have been enabled already. clk: failed to reparent uart1 to sys_pll1_80m: -16 Instead of pre-initializing all UARTS, scan the device tree to see which UART clocks are associated to stdout, and only enable those UART clocks if it's needed early. This will move initialization of the remaining clocks until after the parenting of the clocks. When the clocks are shutdown, this mechanism will also disable any clocks that were pre-initialized. Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection") Suggested-by: Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2020-12-21Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds1-15/+12
Pull clk updates from Stephen Boyd: "The core framework got some nice improvements this time around. We gained the ability to get struct clk pointers from a struct clk_hw so that clk providers can consume the clks they provide, if they need to do something like that. This has been a long missing part of the clk provider API that will help us move away from exposing a struct clk pointer in the struct clk_hw. Tracepoints are added for the clk_set_rate() "range" functions, similar to the tracepoints we already have for clk_set_rate() and we added a column to debugfs to help developers understand the hardware enable state of clks in case firmware or bootloader state is different than what is expected. Overall the core changes are mostly improving the clk driver writing experience. At the driver level, we have the usual collection of driver updates and new drivers for new SoCs. This time around the Qualcomm folks introduced a good handful of clk drivers for various parts of three or four SoCs. The SiFive folks added a new clk driver for their FU740 SoCs, coming in second on the diffstat and then Atmel AT91 and Amlogic SoCs had lots of work done after that for various new features. One last thing to note in the driver area is that the i.MX driver has gained a new binding to support SCU clks after being on the list for many months. It uses a two cell binding which is sort of rare in clk DT bindings. Beyond that we have the usual set of driver fixes and tweaks that come from more testing and finding out that some configuration was wrong or that a driver could support being built as a module. Summary: Core: - Add some trace points for clk_set_rate() "range" functions - Add hardware enable information to clk_summary debugfs - Replace clk-provider.h with of_clk.h when possible - Add devm variant of clk_notifier_register() - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw New Drivers: - Bindings for Canaan K210 SoC clks - Support for SiFive FU740 PRCI - Camera clks on Qualcomm SC7180 SoCs - GCC and RPMh clks on Qualcomm SDX55 SoCs - RPMh clks on Qualcomm SM8350 SoCs - LPASS clks on Qualcomm SM8250 SoCs Updates: - DVFS support for AT91 clk driver - Update git repo branch for Renesas clock drivers - Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U - Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E - Stop using __raw_*() I/O accessors in Renesas clk drivers - One more conversion of DT bindings to json-schema - Make i.MX clk-gate2 driver more flexible - New two cell binding for i.MX SCU clks - Drop of_match_ptr() in i.MX8 clk drivers - Add arch dependencies for Rockchip clk drivers - Fix i2s on Rockchip rk3066 - Add MIPI DSI clks on Amlogic axg and g12 SoCs - Support modular builds of Amlogic clk drivers - Fix an Amlogic Video PLL clock dependency - Samsung Kconfig dependencies updates for better compile test coverage - Refactoring of the Samsung PLL clocks driver - Small Tegra driver cleanups - Minor fixes to Ingenic and VC5 clk drivers - Cleanup patches to remove unused variables and plug memory leaks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) dt-binding: clock: Document canaan,k210-clk bindings dt-bindings: Add Canaan vendor prefix clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts" clk: ingenic: Fix divider calculation with div tables clk: sunxi-ng: Make sure divider tables have sentinel clk: s2mps11: Fix a resource leak in error handling paths in the probe function clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9 clk: si5351: Wait for bit clear after PLL reset clk: at91: sam9x60: remove atmel,osc-bypass support clk: at91: sama7g5: register cpu clock clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics clk: at91: clk-master: add 5th divisor for mck master clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: fix compilation error ...
2020-11-04clk: imx8m: fix bus critical clk registrationPeng Fan1-0/+5
noc/axi/ahb are bus clk, not peripheral clk. Since peripheral clk has a limitation that for peripheral clock slice, IP clock slices must be stopped to change the clock source. However if the bus clk is marked as critical clk peripheral, the assigned clock parent operation will fail. So we added CLK_SET_PARENT_GATE flag to avoid glitch. And add imx8m_clk_hw_composite_bus_critical for bus critical clock usage Fixes: 936c383673b9e ("clk: imx: fix composite peripheral flags") Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reported-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1604229834-25594-1-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-03clk: imx: gate2: Add cgr_mask for more flexible number of control bitsAbel Vesa1-12/+12
On some i.MX8 platforms, there are HW gates that share the same bit. So in order to make this clock type more usable, use a mask to specify how many bits belong to those HW gates. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-03clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special caseAbel Vesa1-4/+1
This was a hack which would allow multiple HW gates to be controlled by a single bit. The only user of this is the imx_dev_clk_hw_gate_shared which is not used anywhere as of now. Basically, complicates the logic of the driver for no reason. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22clk: imx: Explicitly include bits.hAnson Huang1-0/+1
It is better to explicitly include the required header file rather then get it through some recursive include. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22clk: imx: Support building i.MX common clock driver as moduleAnson Huang1-0/+6
There are more and more requirements of building SoC specific drivers as modules, add support for building i.MX common clock driver as module to meet the requirement. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-21clk: imx: add imx8m_clk_hw_composite_busPeng Fan1-0/+7
Introduce imx8m_clk_hw_composite_bus api for bus clk root slice usage. Because the mux switch sequence issue, we could not reuse Peripheral Clock Slice code, need use composite specific mux operation. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-29clk: imx: Add helpers for passing the device as argumentAbel Vesa1-0/+29
All the imx clocks that need to be registered by the audiomix need to pass on the device so that the runtime PM support could work properly. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-29clk: imx: pll14xx: Add the device as argument when registeringAbel Vesa1-3/+10
In order to allow runtime PM, the device needs to be passed on to the register function. Audiomix clock controller, used on i.MX8MP and future platforms, registers a pll14xx and has runtime PM support. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-29clk: imx: gate2: Allow single bit gating clockAbel Vesa1-0/+13
Audiomix on i.MX8MP registers two gates that share the same enable count but use the same bit to control the gate instead of two bits. By adding the flag IMX_CLK_GATE2_SINGLE_BIT we allow the gate2 to use the generic gate ops for enable, disable and is_enabled. For the disable_unused, nothing happens if this flag is specified. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-14clk: imx: composite-8m: add imx8m_clk_hw_composite_corePeng Fan1-2/+11
There are several clock slices, current composite code only support bus/ip clock slices, it could not support core slice. So introduce a new API imx8m_clk_hw_composite_core to support core slice. To core slice, post divider with 3 bits width and no pre divider. Other fields are same as bus/ip slices. Add a flag IMX_COMPOSITE_CORE for the usecase. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based APIAnson Huang1-2/+5
Switch the imx_clk_gate4_flags() function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: gate3: Switch to clk_hw based APIPeng Fan1-2/+5
Switch the imx_clk_hw_gate3_flags function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: add hw API imx_clk_hw_mux2_flagsPeng Fan1-0/+10
Introduce hw based API imx_clk_hw_mux2_flags, then we could convert i.MX8MN clk driver to use hw based APIs. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: add imx_unregister_hw_clocksPeng Fan1-0/+1
There is a non hw API based imx_unregister_clocks to unregister clocks when of_clk_add_provider failed. Add a hw API based imx_unregister_hw_clocks when of_clk_add_hw_provider failed. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: clk-composite-8m: Switch to clk_hw based APIPeng Fan1-7/+22
Switch the imx8m_clk_hw_composite_flags function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: clk-pll14xx: Switch to clk_hw based APIPeng Fan1-0/+7
Switch the imx_clk_pll14xx function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-11clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw basedAbel Vesa1-1/+1
Renaming the imx_clk_divider_gate register function to imx_clk_hw_divider_gate to be more obvious it is clk_hw based. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-11clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw basedAbel Vesa1-1/+1
Renaming the imx_clk_pfdv2 register function to imx_clk_hw_pfdv2 to be more obvious it is clk_hw based. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-11clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw basedAbel Vesa1-1/+1
Renaming the imx_clk_pllv4 register function to imx_clk_hw_pllv4 to be more obvious it is clk_hw based. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-11clk: imx: Rename sccg and frac pll register to suggest clk_hwAbel Vesa1-2/+10
Renaming the imx_clk_frac_pll and imx_clk_sccg_pll register functions to imx_clk_hw_frac_pll, respectively imx_clk_hw_sccg_pll to be more obvious that they are clk_hw based. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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