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path: root/drivers/clk/renesas/rzv2h-cpg.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-04-22clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validationLad Prabhakar1-3/+6
2025-04-22clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()Lad Prabhakar1-1/+2
2025-04-22clk: renesas: rzv2h: Support static dividers without RMWBiju Das1-1/+4
2025-04-22clk: renesas: rzv2h: Add macro for defining static dividersLad Prabhakar1-0/+3
2025-04-22clk: renesas: rzv2h: Add support for static mux clocksLad Prabhakar1-0/+21
2025-04-22clk: renesas: rzv2h: Fix a typoBiju Das1-1/+1
2025-04-14clk: renesas: rzv2h: Add support for RZ/V2N SoCLad Prabhakar1-0/+6
2025-04-14clk: renesas: rzv2h: Sort compatible list based on SoC part numberLad Prabhakar1-6/+6
2025-04-14clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()Tommaso Merciai1-19/+15
2025-04-14clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate()Tommaso Merciai1-6/+0
2025-04-08clk: renesas: rzv2h: Rename PLL field macros for consistencyLad Prabhakar1-7/+7
2025-04-08clk: renesas: rzv2h: Add support for enabling PLLsLad Prabhakar1-0/+56
2025-04-08clk: renesas: rzv2h: Remove unused `type` field from `struct pll_clk`Lad Prabhakar1-2/+0
2025-04-08clk: renesas: rzv2h: Refactor PLL configuration handlingLad Prabhakar1-5/+8
2025-03-06clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1Biju Das1-6/+6
2025-02-18clk: renesas: rzv2h: Update error messageLad Prabhakar1-2/+2
2025-01-07clk: renesas: rzv2h: Add support for RZ/G3E SoCBiju Das1-0/+6
2025-01-07clk: renesas: rzv2h: Add MSTOP supportBiju Das1-21/+125
2024-12-10clk: renesas: rzv2h: Add selective Runtime PM support for clocksLad Prabhakar1-4/+40
2024-09-02clk: renesas: rzv2h: Add support for dynamic switching divider clocksLad Prabhakar1-1/+164
2024-08-20clk: renesas: Add RZ/V2H(P) CPG driverLad Prabhakar1-0/+6
2024-08-02clk: renesas: Add family-specific clock driver for RZ/V2H(P)Lad Prabhakar1-0/+684