| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2025-05-14 | clk: sunxi-ng: d1: Add missing divider for MMC mod clocks |   Andre Przywara | 1 | -19/+25 |
| 2024-12-02 | module: Convert symbol namespace to string literal |   Peter Zijlstra | 1 | -1/+1 |
| 2024-11-02 | clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset | Andre Przywara | 1 | -1/+1 |
| 2024-10-25 | clk: sunxi-ng: Constify struct ccu_reset_map |   Christophe JAILLET | 1 | -1/+1 |
| 2024-06-04 | clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros |   Jeff Johnson | 1 | -0/+1 |
| 2024-04-15 | clk: sunxi-ng: fix module autoloading |   Krzysztof Kozlowski | 1 | -0/+1 |
| 2023-01-08 | clk: sunxi-ng: d1: Add CAN bus gates and resets |   Fabien Poussin | 1 | -0/+11 |
| 2023-01-08 | clk: sunxi-ng: d1: Mark cpux clock as critical |   András Szemző | 1 | -1/+1 |
| 2022-08-25 | clk: sunxi-ng: d1: Limit PLL rates to stable ranges |   Samuel Holland | 1 | -0/+8 |
| 2021-11-23 | clk: sunxi-ng: Add support for the D1 SoC clocks | Samuel Holland | 1 | -0/+1390 |
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index : wireguard-linux | |
| WireGuard for the Linux kernel | Jason A. Donenfeld |
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