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2025-09-12clk: sunxi-ng: sun6i-rtc: Add A523 specificsChen-Yu Tsai1-0/+11
2025-09-11clk: renesas: r9a09g056: Add clock and reset entries for I3CLad Prabhakar1-0/+8
2025-09-11clk: renesas: r9a09g057: Add clock and reset entries for I3CLad Prabhakar1-0/+8
2025-09-11clk: tegra: Add DFLL DVCO reset control for Tegra114Svyatoslav Ryhel2-6/+26
2025-09-11dt-bindings: clock: tegra30: Add IDs for CSI pad clocksSvyatoslav Ryhel1-0/+1
2025-09-10clk: sunxi-ng: mp: Fix dual-divider clock rate readbackChen-Yu Tsai1-1/+1
2025-09-09clk: qcom: dispcc-glymur: Constify 'struct qcom_cc_desc'Imran Shaik1-1/+1
2025-09-08clk: scmi: migrate round_rate() to determine_rate()Brian Masney1-19/+16
2025-09-08clk: ti: fapll: convert from round_rate() to determine_rate()Brian Masney1-21/+27
2025-09-08clk: ti: dra7-atl: convert from round_rate() to determine_rate()Brian Masney1-5/+7
2025-09-08clk: ti: divider: convert from round_rate() to determine_rate()Brian Masney1-5/+7
2025-09-08clk: ti: composite: convert from round_rate() to determine_rate()Brian Masney1-3/+3
2025-09-08clk: ti: dpll: convert from round_rate() to determine_rate()Brian Masney5-81/+53
2025-09-08clk: ti: dpll: change error return from ~0 to -EINVALBrian Masney1-4/+4
2025-09-08clk: ti: dpll: remove round_rate() in favor of determine_rate()Brian Masney1-6/+0
2025-09-08clk: tegra: tegra210-emc: convert from round_rate() to determine_rate()Brian Masney1-8/+16
2025-09-08clk: tegra: super: convert from round_rate() to determine_rate()Brian Masney1-8/+1
2025-09-08clk: tegra: pll: convert from round_rate() to determine_rate()Brian Masney1-21/+31
2025-09-08clk: tegra: periph: divider: convert from round_rate() to determine_rate()Brian Masney1-7/+1
2025-09-08clk: tegra: divider: convert from round_rate() to determine_rate()Brian Masney1-10/+18
2025-09-08clk: tegra: audio-sync: convert from round_rate() to determine_rate()Brian Masney1-5/+5
2025-09-08clk: fixed-factor: drop round_rate() clk opsBrian Masney1-16/+0
2025-09-08clk: divider: remove round_rate() in favor of determine_rate()Brian Masney1-23/+0
2025-09-08clk: visconti: pll: convert from round_rate() to determine_rate()Brian Masney1-6/+11
2025-09-08clk: versatile: vexpress-osc: convert from round_rate() to determine_rate()Brian Masney1-8/+8
2025-09-08clk: versatile: icst: convert from round_rate() to determine_rate()Brian Masney1-27/+45
2025-09-08clk: versaclock7: convert from round_rate() to determine_rate()Brian Masney1-12/+18
2025-09-08clk: versaclock5: convert from round_rate() to determine_rate()Brian Masney1-31/+40
2025-09-08clk: ux500: prcmu: convert from round_rate() to determine_rate()Brian Masney1-6/+8
2025-09-08clk: spear: vco-pll: convert from round_rate() to determine_rate()Brian Masney1-9/+14
2025-09-08clk: spear: gpt-synth: convert from round_rate() to determine_rate()Brian Masney1-5/+7
2025-09-08clk: spear: frac-synth: convert from round_rate() to determine_rate()Brian Masney1-5/+7
2025-09-08clk: spear: aux-synth: convert from round_rate() to determine_rate()Brian Masney1-5/+7
2025-09-08clk: sp7021: convert from round_rate() to determine_rate()Brian Masney1-10/+12
2025-09-08clk: rockchip: pll: convert from round_rate() to determine_rate()Brian Masney1-9/+14
2025-09-08clk: rockchip: ddr: convert from round_rate() to determine_rate()Brian Masney1-6/+7
2025-09-08clk: qcom: regmap-divider: convert from round_rate() to determine_rate()Brian Masney1-10/+17
2025-09-08clk: mvebu: dove-divider: convert from round_rate() to determine_rate()Brian Masney1-8/+8
2025-09-08clk: mvebu: cpu: convert from round_rate() to determine_rate()Brian Masney1-5/+7
2025-09-08clk: mvebu: corediv: convert from round_rate() to determine_rate()Brian Masney1-8/+10
2025-09-08clk: mvebu: armada-37xx-periph: convert from round_rate() to determine_rate()Brian Masney1-6/+9
2025-09-08clk: mvebu: ap-cpu-clk: convert from round_rate() to determine_rate()Brian Masney1-5/+7
2025-09-08clk: mstar: msc313-cpupll: convert from round_rate() to determine_rate()Brian Masney1-8/+10
2025-09-08clk: microchip: core: convert from round_rate() to determine_rate()Brian Masney1-17/+27
2025-09-08clk: mediatek: pll: convert from round_rate() to determine_rate()Brian Masney3-8/+10
2025-09-08clk: hsdk-pll: convert from round_rate() to determine_rate()Brian Masney1-5/+7
2025-09-08clk: cdce706: convert from round_rate() to determine_rate()Brian Masney1-7/+9
2025-09-08clk: bm1880: convert from round_rate() to determine_rate()Brian Masney1-8/+13
2025-09-08clk: bcm: iproc-asiu: convert from round_rate() to determine_rate()Brian Masney1-10/+15
2025-09-08clk: axs10x: pll_clock: convert from round_rate() to determine_rate()Brian Masney1-5/+7
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