unifdef CPU_ARMv7 and ARM_ARCH_7

ok kettenis@ patrick@

14 files changed, 21 insertions, 418 deletions

diff --git a/sys/arch/arm/arm/bcopyinout.S b/sys/arch/arm/arm/bcopyinout.S
index 7ee27b5d9b6..9a7d11865c0 100644
--- a/sys/arch/arm/arm/bcopyinout.S
+++ b/sys/arch/arm/arm/bcopyinout.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bcopyinout.S,v 1.6 2016/09/21 11:33:05 kettenis Exp $	*/
+/*	$OpenBSD: bcopyinout.S,v 1.7 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: bcopyinout.S,v 1.13 2003/10/31 16:54:05 scw Exp $	*/
 
 /*
@@ -84,12 +84,8 @@ ENTRY(copyin)
 
 	SAVE_REGS
 
-#ifdef CPU_ARMv7
 	/* Get curcpu from TPIDRPRW. */
 	mrc	CP15_TPIDRPRW(r4)
-#else
-	ldr	r4, .Lcpu_info_primary
-#endif
 	ldr	r4, [r4, #CI_CURPCB]
 
 	ldr	r5, [r4, #PCB_ONFAULT]
@@ -303,12 +299,8 @@ ENTRY(copyout)
 
 	SAVE_REGS
 
-#ifdef CPU_ARMv7
 	/* Get curcpu from TPIDRPRW. */
 	mrc	CP15_TPIDRPRW(r4)
-#else
-	ldr	r4, .Lcpu_info_primary
-#endif
 	ldr	r4, [r4, #CI_CURPCB]
 
 	ldr	r5, [r4, #PCB_ONFAULT]
@@ -512,12 +504,8 @@ ENTRY(kcopy)
 
 	SAVE_REGS
 
-#ifdef CPU_ARMv7
 	/* Get curcpu from TPIDRPRW. */
 	mrc	CP15_TPIDRPRW(r4)
-#else
-	ldr	r4, .Lcpu_info_primary
-#endif
 	ldr	r4, [r4, #CI_CURPCB]
 
 	ldr	r5, [r4, #PCB_ONFAULT]
@@ -700,12 +688,8 @@ ENTRY(kcopy)
  * else EFAULT if a page fault occurred.
  */
 ENTRY(badaddr_read_1)
-#ifdef CPU_ARMv7
 	/* Get curcpu from TPIDRPRW. */
 	mrc	CP15_TPIDRPRW(r2)
-#else
-	ldr	r2, .Lcpu_info_primary
-#endif
 	ldr	r2, [r2, #CI_CURPCB]
 	ldr	ip, [r2, #PCB_ONFAULT]
 	adr	r3, 1f
@@ -729,12 +713,8 @@ ENTRY(badaddr_read_1)
  * else EFAULT if a page fault occurred.
  */
 ENTRY(badaddr_read_2)
-#ifdef CPU_ARMv7
 	/* Get curcpu from TPIDRPRW. */
 	mrc	CP15_TPIDRPRW(r2)
-#else
-	ldr	r2, .Lcpu_info_primary
-#endif
 	ldr	r2, [r2, #CI_CURPCB]
 	ldr	ip, [r2, #PCB_ONFAULT]
 	adr	r3, 1f
@@ -758,12 +738,8 @@ ENTRY(badaddr_read_2)
  * else EFAULT if a page fault occurred.
  */
 ENTRY(badaddr_read_4)
-#ifdef CPU_ARMv7
 	/* Get curcpu from TPIDRPRW. */
 	mrc	CP15_TPIDRPRW(r2)
-#else
-	ldr	r2, .Lcpu_info_primary
-#endif
 	ldr	r2, [r2, #CI_CURPCB]
 	ldr	ip, [r2, #PCB_ONFAULT]
 	adr	r3, 1f
diff --git a/sys/arch/arm/arm/bus_space_asm_generic.S b/sys/arch/arm/arm/bus_space_asm_generic.S
index 1a2c627508b..97b71a5cecc 100644
--- a/sys/arch/arm/arm/bus_space_asm_generic.S
+++ b/sys/arch/arm/arm/bus_space_asm_generic.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bus_space_asm_generic.S,v 1.4 2016/03/22 23:35:01 patrick Exp $	*/
+/*	$OpenBSD: bus_space_asm_generic.S,v 1.5 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: bus_space_asm_generic.S,v 1.3 2003/03/27 19:46:14 mycroft Exp $	*/
 
 /*
@@ -50,11 +50,9 @@ ENTRY(generic_bs_r_1)
 	ldrb	r0, [r1, r2]
 	mov	pc, lr
 
-#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_r_2)
 	ldrh	r0, [r1, r2]
 	mov	pc, lr
-#endif
 
 ENTRY(generic_bs_r_4)
 	ldr	r0, [r1, r2]
@@ -68,11 +66,9 @@ ENTRY(generic_bs_w_1)
 	strb	r3, [r1, r2]
 	mov	pc, lr
 
-#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_w_2)
 	strh	r3, [r1, r2]
 	mov	pc, lr
-#endif
 
 ENTRY(generic_bs_w_4)
 	str	r3, [r1, r2]
@@ -96,7 +92,6 @@ ENTRY(generic_bs_rm_1)
 
 	mov	pc, lr
 
-#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_rm_2)
 	add	r0, r1, r2
 	mov	r1, r3
@@ -110,7 +105,6 @@ ENTRY(generic_armv4_bs_rm_2)
 	bne	1b
 
 	mov	pc, lr
-#endif
 
 ENTRY(generic_bs_rm_4)
 	add	r0, r1, r2
@@ -144,7 +138,6 @@ ENTRY(generic_bs_wm_1)
 
 	mov	pc, lr
 
-#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_wm_2)
 	add	r0, r1, r2
 	mov	r1, r3
@@ -158,7 +151,6 @@ ENTRY(generic_armv4_bs_wm_2)
 	bne	1b
 
 	mov	pc, lr
-#endif
 
 ENTRY(generic_bs_wm_4)
 	add	r0, r1, r2
@@ -192,7 +184,6 @@ ENTRY(generic_bs_rr_1)
 
 	mov	pc, lr
 
-#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_rr_2)
 	add	r0, r1, r2
 	mov	r1, r3
@@ -206,7 +197,6 @@ ENTRY(generic_armv4_bs_rr_2)
 	bne	1b
 
 	mov	pc, lr
-#endif
 
 ENTRY(generic_bs_rr_4)
 	add	r0, r1, r2
@@ -240,7 +230,6 @@ ENTRY(generic_bs_wr_1)
 
 	mov	pc, lr
 
-#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_wr_2)
 	add	r0, r1, r2
 	mov	r1, r3
@@ -254,7 +243,6 @@ ENTRY(generic_armv4_bs_wr_2)
 	bne	1b
 
 	mov	pc, lr
-#endif
 
 ENTRY(generic_bs_wr_4)
 	add	r0, r1, r2
@@ -287,7 +275,6 @@ ENTRY(generic_bs_sr_1)
 
 	mov	pc, lr
 
-#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_sr_2)
 	add	r0, r1, r2
 	mov	r1, r3
@@ -300,7 +287,6 @@ ENTRY(generic_armv4_bs_sr_2)
 	bne	1b
 
 	mov	pc, lr
-#endif
 
 ENTRY(generic_bs_sr_4)
 	add	r0, r1, r2
@@ -319,7 +305,6 @@ ENTRY(generic_bs_sr_4)
  * copy region
  */
 
-#if (ARM_ARCH_5 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_c_2)
 	add	r0, r1, r2
 	ldr	r2, [sp, #0]
@@ -349,4 +334,3 @@ ENTRY(generic_armv4_bs_c_2)
 	bne	3b
 
 	mov	pc, lr
-#endif
diff --git a/sys/arch/arm/arm/copystr.S b/sys/arch/arm/arm/copystr.S
index 3c26de37bf5..e38f2903955 100644
--- a/sys/arch/arm/arm/copystr.S
+++ b/sys/arch/arm/arm/copystr.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: copystr.S,v 1.7 2016/09/21 11:33:05 kettenis Exp $	*/
+/*	$OpenBSD: copystr.S,v 1.8 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: copystr.S,v 1.8 2002/10/13 14:54:48 bjh21 Exp $	*/
 
 /*
@@ -105,12 +105,8 @@ ENTRY(copyinstr)
 	moveq	r0, #ENAMETOOLONG
 	beq	2f
 
-#ifdef CPU_ARMv7
 	/* Get curcpu from TPIDRPRW. */
 	mrc	CP15_TPIDRPRW(r4)
-#else
-	ldr	r4, .Lcpu_info_primary
-#endif
 	ldr	r4, [r4, #CI_CURPCB]
 
 #ifdef DEBUG
@@ -157,12 +153,8 @@ ENTRY(copyoutstr)
 	moveq	r0, #ENAMETOOLONG
 	beq	2f
 
-#ifdef CPU_ARMv7
 	/* Get curcpu from TPIDRPRW. */
 	mrc	CP15_TPIDRPRW(r4)
-#else
-	ldr	r4, .Lcpu_info_primary
-#endif
 	ldr	r4, [r4, #CI_CURPCB]
 
 #ifdef DEBUG
diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c
index 1fd96fb1a96..b1de93b1c6b 100644
--- a/sys/arch/arm/arm/cpufunc.c
+++ b/sys/arch/arm/arm/cpufunc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.c,v 1.49 2017/01/02 00:51:18 jsg Exp $	*/
+/*	$OpenBSD: cpufunc.c,v 1.50 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $	*/
 
 /*
@@ -78,7 +78,6 @@ int	arm_dcache_align_mask;
 /* 1 == use cpu_sleep(), 0 == don't */
 int cpu_do_powersave;
 
-#ifdef CPU_ARMv7
 struct cpu_functions armv7_cpufuncs = {
 	/* CPU functions */
 
@@ -135,7 +134,6 @@ struct cpu_functions armv7_cpufuncs = {
 	armv7_context_switch,		/* context_switch	*/
 	armv7_setup			/* cpu setup		*/
 };
-#endif /* CPU_ARMv7 */
 
 /*
  * Global constants also used by locore.s
@@ -149,7 +147,6 @@ int	arm_icache_min_line_size = 32;
 int	arm_dcache_min_line_size = 32;
 int	arm_idcache_min_line_size = 32;
 
-#ifdef CPU_ARMv7
 void arm_get_cachetype_cp15v7 (void);
 int	arm_dcache_l2_nsets;
 int	arm_dcache_l2_assoc;
@@ -265,6 +262,7 @@ armv7_idcache_wbinv_all()
 	__asm volatile("mcr	p15, 0, r0, c7, c5, 0" :: "r" (arg));
 	armv7_dcache_wbinv_all();
 }
+
 /* brute force cache flushing */
 void
 armv7_dcache_wbinv_all()
@@ -305,7 +303,6 @@ armv7_dcache_wbinv_all()
 
 	/* L2 cache flushing removed. Our current L2 caches are separate. */
 }
-#endif /* CPU_ARMv7 */
 
 
 /*
@@ -323,7 +320,6 @@ set_cpufuncs()
 	 * CPU type where we want to use it by default, then we set it.
 	 */
 
-#ifdef CPU_ARMv7
 	if ((cputype & CPU_ID_ARCH_MASK) == CPU_ID_ARCH_CPUID) {
 		uint32_t mmfr0;
 
@@ -351,7 +347,6 @@ set_cpufuncs()
 			return 0;
 		}
 	}
-#endif /* CPU_ARMv7 */
 	/*
 	 * Bzzzz. And the answer was ...
 	 */
@@ -363,7 +358,6 @@ set_cpufuncs()
  * CPU Setup code
  */
 
-#ifdef CPU_ARMv7
 void
 armv7_setup()
 {
@@ -437,4 +431,3 @@ armv7_setup()
 	/* And again. */
 	cpu_idcache_wbinv_all();
 }
-#endif	/* CPU_ARMv7 */
diff --git a/sys/arch/arm/arm/fault.c b/sys/arch/arm/arm/fault.c
index 788469b6ffa..9d86ceca986 100644
--- a/sys/arch/arm/arm/fault.c
+++ b/sys/arch/arm/arm/fault.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fault.c,v 1.25 2016/10/22 17:48:41 patrick Exp $	*/
+/*	$OpenBSD: fault.c,v 1.26 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: fault.c,v 1.46 2004/01/21 15:39:21 skrll Exp $	*/
 
 /*
@@ -135,24 +135,6 @@ extern int dab_access(trapframe_t *, u_int, u_int, struct proc *,
     struct sigdata *sd);
 
 static const struct data_abort data_aborts[] = {
-#ifndef CPU_ARMv7
-	{dab_fatal,	"Vector Exception"},
-	{dab_align,	"Alignment Fault 1"},
-	{dab_fatal,	"Terminal Exception"},
-	{dab_align,	"Alignment Fault 3"},
-	{dab_buserr,	"External Linefetch Abort (S)"},
-	{NULL,		"Translation Fault (S)"},
-	{dab_buserr,	"External Linefetch Abort (P)"},
-	{NULL,		"Translation Fault (P)"},
-	{dab_buserr,	"External Non-Linefetch Abort (S)"},
-	{NULL,		"Domain Fault (S)"},
-	{dab_buserr,	"External Non-Linefetch Abort (P)"},
-	{NULL,		"Domain Fault (P)"},
-	{dab_buserr,	"External Translation Abort (L1)"},
-	{NULL,		"Permission Fault (S)"},
-	{dab_buserr,	"External Translation Abort (L2)"},
-	{NULL,		"Permission Fault (P)"}
-#else
 	{dab_fatal,	"V7 fault 00000"},
 	{dab_align,	"Alignment fault"},
 	{dab_fatal,	"Debug event"},
@@ -185,7 +167,6 @@ static const struct data_abort data_aborts[] = {
 	{dab_fatal,	"V7 fault 11101"},
 	{dab_buserr,	"Synchronous parity error on translation table walk (L2)"},
 	{NULL,		"V7 fault 11111"},
-#endif
 };
 
 /* Determine if 'ftyp' is a permission fault */
@@ -210,11 +191,7 @@ data_abort_handler(trapframe_t *tf)
 	/* Grab FAR/FSR before enabling interrupts */
 	far = cpu_dfar();
 	fsr = cpu_dfsr();
-#ifndef CPU_ARMv7
-	ftyp = FAULT_TYPE(fsr);
-#else
 	ftyp = FAULT_TYPE_V7(fsr);
-#endif
 
 	/* Update vmmeter statistics */
 	uvmexp.traps++;
@@ -328,54 +305,7 @@ data_abort_handler(trapframe_t *tf)
 #endif
 	}
 
-#ifndef CPU_ARMv7
-	/*
-	 * We need to know whether the page should be mapped
-	 * as R or R/W. The MMU does not give us the info as
-	 * to whether the fault was caused by a read or a write.
-	 *
-	 * However, we know that a permission fault can only be
-	 * the result of a write to a read-only location, so
-	 * we can deal with those quickly.
-	 *
-	 * Otherwise we need to disassemble the instruction
-	 * responsible to determine if it was a write.
-	 */
-	if (IS_PERMISSION_FAULT(fsr))
-		ftype = PROT_WRITE; 
-	else {
-		u_int insn = *(u_int *)tf->tf_pc;
-
-		if (((insn & 0x0c100000) == 0x04000000) ||	/* STR/STRB */
-		    ((insn & 0x0e1000b0) == 0x000000b0) ||	/* STRH/STRD */
-		    ((insn & 0x0a100000) == 0x08000000))	/* STM/CDT */
-			ftype = PROT_WRITE; 
-		else
-		if ((insn & 0x0fb00ff0) == 0x01000090)		/* SWP */
-			ftype = PROT_READ | PROT_WRITE; 
-		else
-			ftype = PROT_READ; 
-	}
-#else
 	ftype = fsr & FAULT_WNR ? PROT_WRITE : PROT_READ;
-#endif
-
-#ifndef CPU_ARMv7
-	/*
-	 * See if the fault is as a result of ref/mod emulation,
-	 * or domain mismatch.
-	 */
-#ifdef DEBUG
-	last_fault_code = fsr;
-#endif
-	if (pmap_fault_fixup(map->pmap, va, ftype, user)) {
-#if 0
-		if (map != kernel_map)
-			p->p_flag &= ~L_SA_PAGEFAULT;
-#endif
-		goto out;
-	}
-#endif
 
 	if (__predict_false(curcpu()->ci_idepth > 0)) {
 		if (pcb->pcb_onfault) {
@@ -415,7 +345,6 @@ data_abort_handler(trapframe_t *tf)
 		dab_fatal(tf, fsr, far, p, NULL);
 	}
 
-
 	sv.sival_ptr = (u_int32_t *)far;
 	if (error == ENOMEM) {
 		printf("UVM: pid %d (%s), uid %d killed: "
@@ -460,18 +389,10 @@ dab_fatal(trapframe_t *tf, u_int fsr, u_int far, struct proc *p,
 	mode = TRAP_USERMODE(tf) ? "user" : "kernel";
 
 	if (p != NULL) {
-#ifndef CPU_ARMv7
-		ftyp = FAULT_TYPE(fsr);
-#else
 		ftyp = FAULT_TYPE_V7(fsr);
-#endif
 		printf("Fatal %s mode data abort: '%s'\n", mode,
 		    data_aborts[ftyp].desc);
 		printf("trapframe: %p\nDFSR=%08x, DFAR=%08x", tf, fsr, far);
-#ifndef CPU_ARMv7
-		if ((fsr & FAULT_IMPRECISE) != 0)
-			printf(" (imprecise)");
-#endif
 		printf(", spsr=%08lx\n", tf->tf_spsr);
 	} else {
 		printf("Fatal %s mode prefetch abort at 0x%08lx\n",
@@ -649,13 +570,8 @@ prefetch_abort_handler(trapframe_t *tf)
 	uvmexp.traps++;
 
 	/* Grab FAR/FSR before enabling interrupts */
-#ifndef CPU_ARMv7
-	far = tf->tf_pc;
-	fsr = 0;
-#else
 	far = cpu_ifar();
 	fsr = cpu_ifsr();
-#endif
 
 	/* Prefetch aborts cannot happen in kernel mode */
 	if (__predict_false(!TRAP_USERMODE(tf)))
@@ -671,13 +587,11 @@ prefetch_abort_handler(trapframe_t *tf)
 
 	p = curproc;
 
-#ifdef CPU_ARMv7
 	/* Invoke access fault handler if appropriate */
 	if (FAULT_TYPE_V7(fsr) == FAULT_ACCESS_2) {
 		dab_access(tf, fsr, far, p, NULL);
 		goto out;
 	}
-#endif
 
 	p->p_addr->u_pcb.pcb_tf = tf;
 
@@ -692,16 +606,6 @@ prefetch_abort_handler(trapframe_t *tf)
 	map = &p->p_vmspace->vm_map;
 	va = trunc_page(far);
 
-#ifndef CPU_ARMv7
-	/*
-	 * See if the pmap can handle this fault on its own...
-	 */
-#ifdef DEBUG
-	last_fault_code = -1;
-#endif
-	if (pmap_fault_fixup(map->pmap, va, PROT_READ | PROT_EXEC, 1))
-		goto out;
-#endif
 
 #ifdef DIAGNOSTIC
 	if (__predict_false(curcpu()->ci_idepth > 0)) {
diff --git a/sys/arch/arm/arm/irq_dispatch.S b/sys/arch/arm/arm/irq_dispatch.S
index 44068760c15..63ce56424db 100644
--- a/sys/arch/arm/arm/irq_dispatch.S
+++ b/sys/arch/arm/arm/irq_dispatch.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: irq_dispatch.S,v 1.12 2016/09/21 11:33:05 kettenis Exp $	*/
+/*	$OpenBSD: irq_dispatch.S,v 1.13 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: irq_dispatch.S,v 1.5 2003/10/30 08:57:24 scw Exp $	*/
 
 /*
@@ -106,11 +106,7 @@ ASENTRY_NP(irq_entry)
 	 *	r5	address of the curcpu struct
 	 *	r6	old value of curcpu()->ci_idepth
 	 */
-#ifdef CPU_ARMv7
 	mrc	CP15_TPIDRPRW(r5)	/* Get curcpu from TPIDRPRW. */
-#else
-	ldr	r5, .Lcpu_info_primary
-#endif
 	mov	r0, sp			/* arg for dispatcher */
 	ldr	r6, [r5, #CI_IDEPTH]
 	add	r1, r6, #1
diff --git a/sys/arch/arm/arm/locore.S b/sys/arch/arm/arm/locore.S
index a142476f2ed..9e393bc3e36 100644
--- a/sys/arch/arm/arm/locore.S
+++ b/sys/arch/arm/arm/locore.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.S,v 1.12 2016/09/24 13:43:25 kettenis Exp $	*/
+/*	$OpenBSD: locore.S,v 1.13 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $	*/
 
 /*
@@ -60,9 +60,7 @@ ASENTRY_NP(start)
 	adr	r1, .Lstart
 	ldmia	r1, {r1, r2, r8, sp}	/* Set initial stack and */
 
-#ifdef CPU_ARMv7
 	mcr	CP15_TPIDRPRW(r8)	/* put curcpu into the TPIDRPRW */
-#endif
 
 	sub	r2, r2, r1		/* get zero init data */
 	mov	r3, #0
diff --git a/sys/arch/arm/include/atomic.h b/sys/arch/arm/include/atomic.h
index 27dddf96e60..0b44702edf4 100644
--- a/sys/arch/arm/include/atomic.h
+++ b/sys/arch/arm/include/atomic.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: atomic.h,v 1.15 2016/05/16 13:18:51 jsg Exp $	*/
+/*	$OpenBSD: atomic.h,v 1.16 2017/01/06 00:06:02 jsg Exp $	*/
 
 /* Public Domain */
 
@@ -7,193 +7,6 @@
 
 #if defined(_KERNEL)
 
-#if !defined(CPU_ARMv7)
-
-#include <arm/cpufunc.h>
-#include <arm/armreg.h>
-
-/*
- * on pre-v6 arm processors, it is necessary to disable interrupts if
- * in the kernel and atomic updates are necessary without full mutexes
- */
-
-static inline unsigned int
-_atomic_cas_uint(volatile unsigned int *uip, unsigned int o, unsigned int n)
-{
-	unsigned int cpsr;
-	unsigned int rv;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	rv = *uip;
-	if (rv == o)
-		*uip = n;
-	restore_interrupts(cpsr);
-
-	return (rv);
-}
-#define atomic_cas_uint(_p, _o, _n) _atomic_cas_uint((_p), (_o), (_n))
-
-static inline unsigned int
-_atomic_cas_ulong(volatile unsigned long *uip, unsigned long o, unsigned long n)
-{
-	unsigned int cpsr;
-	unsigned long rv;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	rv = *uip;
-	if (rv == o)
-		*uip = n;
-	restore_interrupts(cpsr);
-
-	return (rv);
-}
-#define atomic_cas_ulong(_p, _o, _n) _atomic_cas_ulong((_p), (_o), (_n))
-
-static inline void *
-_atomic_cas_ptr(volatile void *uip, void *o, void *n)
-{
-	unsigned int cpsr;
-	void * volatile *uipp = (void * volatile *)uip;
-	void *rv;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	rv = *uipp;
-	if (rv == o)
-		*uipp = n;
-	restore_interrupts(cpsr);
-
-	return (rv);
-}
-#define atomic_cas_ptr(_p, _o, _n) _atomic_cas_ptr((_p), (_o), (_n))
-
-static inline unsigned int
-_atomic_swap_uint(volatile unsigned int *uip, unsigned int n)
-{
-	unsigned int cpsr;
-	unsigned int rv;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	rv = *uip;
-	*uip = n;
-	restore_interrupts(cpsr);
-
-	return (rv);
-}
-#define atomic_swap_uint(_p, _n) _atomic_swap_uint((_p), (_n))
-
-static inline unsigned long
-_atomic_swap_ulong(volatile unsigned long *uip, unsigned long n)
-{
-	unsigned int cpsr;
-	unsigned long rv;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	rv = *uip;
-	*uip = n;
-	restore_interrupts(cpsr);
-
-	return (rv);
-}
-#define atomic_swap_ulong(_p, _n) _atomic_swap_ulong((_p), (_n))
-
-static inline void *
-_atomic_swap_ptr(volatile void *uip, void *n)
-{
-	unsigned int cpsr;
-	void * volatile *uipp = (void * volatile *)uip;
-	void *rv;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	rv = *uipp;
-	*uipp = n;
-	restore_interrupts(cpsr);
-
-	return (rv);
-}
-#define atomic_swap_ptr(_p, _n) _atomic_swap_ptr((_p), (_n))
-
-static inline unsigned int
-_atomic_add_int_nv(volatile unsigned int *uip, unsigned int v)
-{
-	unsigned int cpsr;
-	unsigned int rv;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	rv = *uip + v;
-	*uip = rv;
-	restore_interrupts(cpsr);
-
-	return (rv);
-}
-#define atomic_add_int_nv(_p, _v) _atomic_add_int_nv((_p), (_v))
-
-static inline unsigned long
-_atomic_add_long_nv(volatile unsigned long *uip, unsigned long v)
-{
-	unsigned int cpsr;
-	unsigned long rv;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	rv = *uip + v;
-	*uip = rv;
-	restore_interrupts(cpsr);
-
-	return (rv);
-}
-#define atomic_add_long_nv(_p, _v) _atomic_add_long_nv((_p), (_v))
-
-static inline unsigned int
-_atomic_sub_int_nv(volatile unsigned int *uip, unsigned int v)
-{
-	unsigned int cpsr;
-	unsigned int rv;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	rv = *uip - v;
-	*uip = rv;
-	restore_interrupts(cpsr);
-
-	return (rv);
-}
-#define atomic_sub_int_nv(_p, _v) _atomic_sub_int_nv((_p), (_v))
-
-static inline unsigned long
-_atomic_sub_long_nv(volatile unsigned long *uip, unsigned long v)
-{
-	unsigned int cpsr;
-	unsigned long rv;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	rv = *uip - v;
-	*uip = rv;
-	restore_interrupts(cpsr);
-
-	return (rv);
-}
-#define atomic_sub_long_nv(_p, _v) _atomic_sub_long_nv((_p), (_v))
-
-static inline void
-atomic_setbits_int(volatile unsigned int *uip, unsigned int v)
-{
-	unsigned int cpsr;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	*uip |= v;
-	restore_interrupts(cpsr);
-}
-
-static inline void
-atomic_clearbits_int(volatile unsigned int *uip, unsigned int v)
-{
-	unsigned int cpsr;
-
-	cpsr = disable_interrupts(PSR_I|PSR_F);
-	*uip &= ~v;
-	restore_interrupts(cpsr);
-}
-
-#else /* !CPU_ARMv7 */
-
 /*
  * Compare and set:
  * ret = *ptr
@@ -363,7 +176,6 @@ def_atomic_dec_nv(_atomic_dec_long_nv, unsigned long)
 #define atomic_dec_int_nv(_p) _atomic_dec_int_nv((_p))
 #define atomic_dec_long_nv(_p) _atomic_dec_long_nv((_p))
 
-
 /*
  * Addition returning the new value
  * *p += v
@@ -465,19 +277,6 @@ atomic_clearbits_int(volatile unsigned int *p, unsigned int v)
 	    : "memory", "cc"
 	);
 }
-#endif /* CPU_ARMv7 */
-
-#if !defined(CPU_ARMv7)
-
-#define __membar() do { __asm __volatile("" ::: "memory"); } while (0)
-
-#define membar_enter()		__membar()
-#define membar_exit()		__membar()
-#define membar_producer()	__membar()
-#define membar_consumer()	__membar()
-#define membar_sync()		__membar()
-
-#else /* !CPU_ARMv7 */
 
 #define __membar(_f) do { __asm __volatile(_f ::: "memory"); } while (0)
 
@@ -490,7 +289,6 @@ atomic_clearbits_int(volatile unsigned int *p, unsigned int v)
 #define virtio_membar_producer()	__membar("dmb st")
 #define virtio_membar_consumer()	__membar("dmb sy")
 #define virtio_membar_sync()		__membar("dmb sy")
-#endif /* CPU_ARMv7 */
 
 #endif /* defined(_KERNEL) */
 #endif /* _ARM_ATOMIC_H_ */
diff --git a/sys/arch/arm/include/cpu.h b/sys/arch/arm/include/cpu.h
index 95828eea212..e82c6a761e2 100644
--- a/sys/arch/arm/include/cpu.h
+++ b/sys/arch/arm/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.42 2017/01/05 16:16:17 patrick Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.43 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: cpu.h,v 1.34 2003/06/23 11:01:08 martin Exp $	*/
 
 /*
@@ -209,7 +209,6 @@ struct cpu_info {
 extern struct cpu_info cpu_info_primary;
 extern struct cpu_info *cpu_info_list;
 
-#ifdef CPU_ARMv7
 static inline struct cpu_info *
 curcpu(void)
 {
@@ -217,9 +216,6 @@ curcpu(void)
 	__asm volatile("mrc	p15, 0, %0, c13, c0, 4" : "=r" (__ci));
 	return (__ci);
 }
-#else
-#define	curcpu()	(&cpu_info_primary)
-#endif
 
 #ifndef MULTIPROCESSOR
 #define cpu_number()	0
diff --git a/sys/arch/arm/include/cpuconf.h b/sys/arch/arm/include/cpuconf.h
index 469585c4a69..e5580ce9778 100644
--- a/sys/arch/arm/include/cpuconf.h
+++ b/sys/arch/arm/include/cpuconf.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpuconf.h,v 1.18 2017/01/04 00:40:49 jsg Exp $	*/
+/*	$OpenBSD: cpuconf.h,v 1.19 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $	*/
 
 /*
@@ -46,26 +46,13 @@
  */
 
 /*
- * Determine which ARM architecture versions are configured.
- */
-#if defined(CPU_ARMv7)
-#define ARM_ARCH_7     1
-#else 
-#define ARM_ARCH_7     0
-#endif
-
-/*
  * Define which MMU classes are configured:
  *
  *      ARM_MMU_V7		v6/v7 MMU with XP bit enabled subpage
  *				protection is not used, TEX/AP is used instead.
  */
 
-#if defined(CPU_ARMv7)
 #define ARM_MMU_V7		1
-#else
-#define ARM_MMU_V7		0
-#endif
 
 #define	ARM_NMMUS		(ARM_MMU_V7)
 
diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h
index 7a824565a01..65da821b49a 100644
--- a/sys/arch/arm/include/cpufunc.h
+++ b/sys/arch/arm/include/cpufunc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.h,v 1.28 2017/01/04 00:40:49 jsg Exp $	*/
+/*	$OpenBSD: cpufunc.h,v 1.29 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $	*/
 
 /*
@@ -218,7 +218,6 @@ u_int	cpufunc_dfar		(void);
 u_int	cpufunc_ifsr		(void);
 u_int	cpufunc_ifar		(void);
 
-#ifdef CPU_ARMv7
 void	armv7_setttb		(u_int);
 
 void	armv7_tlb_flushID_SE	(u_int);
@@ -252,7 +251,6 @@ extern unsigned armv7_dcache_sets_max;
 extern unsigned armv7_dcache_sets_inc;
 extern unsigned armv7_dcache_index_max;
 extern unsigned armv7_dcache_index_inc;
-#endif
 
 #define tlb_flush	cpu_tlb_flushID
 #define setttb		cpu_setttb
diff --git a/sys/arch/arm/include/frame.h b/sys/arch/arm/include/frame.h
index dd68dcc5d99..97382ef521c 100644
--- a/sys/arch/arm/include/frame.h
+++ b/sys/arch/arm/include/frame.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: frame.h,v 1.11 2016/10/22 17:48:41 patrick Exp $	*/
+/*	$OpenBSD: frame.h,v 1.12 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: frame.h,v 1.9 2003/12/01 08:48:33 scw Exp $	*/
 
 /*
@@ -213,11 +213,6 @@ struct frame {
  * way to take care of both issues and to make sure that the kernel
  * and userland do not leave any outstanding reserves active.
  */
-#if defined(CPU_ARMv7)
-#define CLREX clrex
-#else
-#define CLREX
-#endif
 
 /*
  * PUSHFRAME - macro to push a trap frame on the stack in the current mode
@@ -225,7 +220,7 @@ struct frame {
  */
 
 #define PUSHFRAME							   \
-	CLREX;								   \
+	clrex;								   \
 	sub	sp, sp, #4;		/* Align the stack */		   \
 	str	lr, [sp, #-4]!;		/* Push the return address */	   \
 	sub	sp, sp, #(4*17);	/* Adjust the stack pointer */	   \
@@ -240,7 +235,7 @@ struct frame {
  */
 
 #define PULLFRAME							   \
-	CLREX;								   \
+	clrex;								   \
 	ldr	r0, [sp], #0x0004;	/* Get the SPSR from stack */	   \
 	msr	spsr_fsxc, r0;						   \
 	ldmia	sp, {r0-r14}^;		/* Restore registers (usr mode) */ \
@@ -258,7 +253,7 @@ struct frame {
  */
 
 #define PUSHFRAMEINSVC							   \
-	CLREX;								   \
+	clrex;								   \
 	stmdb	sp, {r0-r3};		/* Save 4 registers */		   \
 	mov	r0, lr;			/* Save xxx32 r14 */		   \
 	mov	r1, sp;			/* Save xxx32 sp */		   \
@@ -289,7 +284,7 @@ struct frame {
  */
 
 #define PULLFRAMEFROMSVCANDEXIT						   \
-	CLREX;								   \
+	clrex;								   \
 	ldr	r0, [sp], #0x0004;	/* Get the SPSR from stack */	   \
 	msr	spsr_fsxc, r0;		/* restore SPSR */		   \
 	ldmia	sp, {r0-r14}^;		/* Restore registers (usr mode) */ \
diff --git a/sys/arch/arm/include/pmap.h b/sys/arch/arm/include/pmap.h
index b7dbf94b640..83c3395f710 100644
--- a/sys/arch/arm/include/pmap.h
+++ b/sys/arch/arm/include/pmap.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.h,v 1.47 2017/01/04 00:40:49 jsg Exp $	*/
+/*	$OpenBSD: pmap.h,v 1.48 2017/01/06 00:06:02 jsg Exp $	*/
 /*	$NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $	*/
 
 /*
@@ -375,9 +375,7 @@ void	pmap_copy_page_generic(struct vm_page *, struct vm_page *);
 void	pmap_zero_page_generic(struct vm_page *);
 
 void	pmap_pte_init_generic(void);
-#if defined(CPU_ARMv7)
 void	pmap_pte_init_armv7(void);
-#endif /* CPU_ARMv7 */
 #endif /* (ARM_MMU_V7) != 0 */
 
 #if ARM_MMU_V7 == 1
@@ -568,10 +566,8 @@ L1_S_PROT(int ku, vm_prot_t pr)
 	else
 		pte = (pr & PROT_WRITE) ? L1_S_PROT_KW : L1_S_PROT_KR;
 
-#ifdef CPU_ARMv7
 	if ((pr & PROT_EXEC) == 0)
 		pte |= L1_S_V7_XN;
-#endif
 
 	return pte;
 }
@@ -585,10 +581,8 @@ L2_L_PROT(int ku, vm_prot_t pr)
 	else
 		pte = (pr & PROT_WRITE) ? L2_L_PROT_KW : L2_L_PROT_KR;
 
-#ifdef CPU_ARMv7
 	if ((pr & PROT_EXEC) == 0)
 		pte |= L2_V7_L_XN;
-#endif
 
 	return pte;
 }
@@ -602,10 +596,8 @@ L2_S_PROT(int ku, vm_prot_t pr)
 	else
 		pte = (pr & PROT_WRITE) ? L2_S_PROT_KW : L2_S_PROT_KR;
 
-#ifdef CPU_ARMv7
 	if ((pr & PROT_EXEC) == 0)
 		pte |= L2_V7_S_XN;
-#endif
 
 	return pte;
 }
diff --git a/sys/arch/arm/mainbus/mainbus.c b/sys/arch/arm/mainbus/mainbus.c
index 30ca099ad27..80a5e508031 100644
--- a/sys/arch/arm/mainbus/mainbus.c
+++ b/sys/arch/arm/mainbus/mainbus.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: mainbus.c,v 1.14 2017/01/03 19:57:01 kettenis Exp $ */
+/* $OpenBSD: mainbus.c,v 1.15 2017/01/06 00:06:02 jsg Exp $ */
 /*
  * Copyright (c) 2016 Patrick Wildt <patrick@blueri.se>
  *
@@ -83,6 +83,8 @@ mainbus_match(struct device *parent, void *cfdata, void *aux)
 }
 
 extern char *hw_prod;
+extern struct bus_space armv7_bs_tag;
+void platform_init_mainbus(struct device *);
 
 void
 mainbus_attach(struct device *parent, struct device *self, void *aux)
@@ -97,14 +99,9 @@ mainbus_attach(struct device *parent, struct device *self, void *aux)
 		return;
 	}
 
-#ifdef CPU_ARMv7
 	arm_intr_init_fdt();
-#endif
 
-#ifdef CPU_ARMv7
-	extern struct bus_space armv7_bs_tag;
 	sc->sc_iot = &armv7_bs_tag;
-#endif
 	sc->sc_dmat = &mainbus_dma_tag;
 	sc->sc_acells = OF_getpropint(OF_peer(0), "#address-cells", 1);
 	sc->sc_scells = OF_getpropint(OF_peer(0), "#size-cells", 1);
@@ -119,10 +116,7 @@ mainbus_attach(struct device *parent, struct device *self, void *aux)
 
 	/* Attach CPU first. */
 	mainbus_legacy_found(self, "cpu");
-#ifdef CPU_ARMv7
-	extern void platform_init_mainbus(struct device *);
 	platform_init_mainbus(self);
-#endif
 
 	/* TODO: Scan for interrupt controllers and attach them first? */